A-port networks: Preserving the timed behavior of synchronous systems for modeling on FPGAs

ACM Transactions on Reconfigurable Technology and Systems

Volumn 2, Issue 3, 2009, Pages

  Pellauer, Michael ^a   Vijayaraghavan, Muralidaran ^a   Adler, Michael ^b   Arvind, ^a   Emer, Joel ^a,b  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Design; Measurement; Performance

Indexed keywords

COMPUTER ARCHITECTS; CYCLE ACCURATE; FINE-GRAINED PARALLELISM; MULTI-CORES; ORDERS OF MAGNITUDE; PERFORMANCE; PERFORMANCE IMPROVEMENTS; PERFORMANCE MODEL; SOFTWARE MODEL; SYNCHRONOUS SYSTEM;

DESIGN; MEASUREMENTS; PARALLEL ARCHITECTURES;

COMPUTER SIMULATION;

EID: 84867422032     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1575774.1575775     Document Type: Article

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