Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 723-728

  Yu, Wang ^a   Hai, Lin ^a   Yang, Huazhong ^a   Rong, Luo ^a   Hui, Wang ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT FUNCTIONALITY; CIRCUIT SLACK UTILIZATION; CIRCUITS AND SYSTEMS; LEAKAGE CURRENT REDUCTION; LEAKAGE OPTIMIZATION; LEAKAGE POWER DISSIPATIONS; MIXED INTEGER LINEAR PROGRAMMING; SLEEP TRANSISTOR PLACEMENT;

LINEAR PROGRAMMING; TRANSISTORS; VLSI CIRCUITS;

LEAKAGE CURRENTS;

EID: 50249151300     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.117     Document Type: Conference Paper

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