USJ process challenges for sub-45 nm CMOS

AIP Conference Proceedings

Volumn 1066, Issue , 2008, Pages 55-62

  Kalra, Pankaj ^a,b   Majhi, Prashant ^a,c   Tseng, Hsing Huang ^a   Larson, Larry ^a   Jammy, Raj ^a,d   Liu, Tsu Jae King ^b  

^a SEMATECH   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c INTEL CORPORATION   (United States)

^d IBM   (United States)

Author keywords

CMOS scaling; Flash anneal; High K; Metal gate; Ultra shallow junctions; USJs

Indexed keywords

EID: 77954274635     PISSN: 0094243X     EISSN: 15517616     Source Type: Conference Proceeding    
DOI: 10.1063/1.3033683     Document Type: Conference Paper

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