LASER anneal to enable ultimate CMOS scaling with PMOS band edge metal gate/high-K stacks

ESSDERC 2006 - Proceedings of the 36th European Solid-State Device Research Conference

Volumn , Issue , 2006, Pages 351-354

  Gilmer, D C ^a   Schaeffer, J K ^a   Taylor, W J ^a   Spencer, G ^a   Triyoso, D H ^a   Raymond, M ^a   Roan, D ^a   Smith, J ^a   Capasso, C ^a   Hegde, R I ^a   Samavedam, S B ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVATION ENERGY; ANNEALING; CMOS INTEGRATED CIRCUITS; MOS DEVICES; STACKING FAULTS;

CMOS SCALING; GATE ELECTRODE; RTP ACTIVATION;

SCALING LAWS;

EID: 77952339255     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSDER.2006.307710     Document Type: Conference Paper

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