Issues and optimization of millisecond anneal process for 45 nm node and beyond

Digest of Technical Papers - Symposium on VLSI Technology

Volumn 2005, Issue , 2005, Pages 142-143

  Adachi, K ^a   Ohuchi, K ^a   Aoki, N ^a   Tsujii, H ^a   Ito, T ^a   Itokawa, H ^a   Matsuo, K ^a   Suguro, K ^a   Honguh, Y ^a   Tamaoki, N ^a   Ishimaru, K ^a   Ishiuchi, H ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

CMOSFET; FLA; LSA and; Millisecond anneal

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LASER APPLICATIONS; LEAKAGE CURRENTS; MOSFET DEVICES; OPTIMIZATION;

CMOSFET; FLA; LSA; MILLISECOND ANNEAL;

NANOTECHNOLOGY;

EID: 33646045529     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/.2005.1469245     Document Type: Conference Paper

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