Ultra-thin chip technology and applications, a new paradigm in silicon technology

Solid-State Electronics

Volumn 54, Issue 9, 2010, Pages 818-829

  Burghartz, Joachim N ^a   Appel, Wolfgang ^a   Harendt, Christine ^a   Rempp, Horst ^a   Richter, Harald ^a   Zimmermann, Martin ^a  

^a Institut fur Mikroelektronik Stuttgart   (Germany)

Author keywords

3D chip stacking; Buried cavity formation; Flexible electronics; Porous silicon; Thin chip singulation; Thin silicon chip fabrication

Indexed keywords

BURIED CAVITY FORMATION; CAVITY FORMATION; CHIP STACKING; SILICON CHIP; SINGULATION; THIN CHIPS;

FLEXIBLE ELECTRONICS; POROUS SILICON; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 77954213333     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2010.04.042     Document Type: Conference Paper

References (38)

1. K. Peterson Silicon as a mechanical material Proc IEEE 70 5 1982 420 457
2. V.P. Ganesh, and C. Lee Overview and emerging challenges in wafer thinning process for handheld applications Proc Int Electr Manuf Technol 2006 20 26
3. M. Koyanagi, T. Nakamura, Y. Yamada, H. Kikuchi, T. Fukushima, and T. Tanaka Three-dimensional integration technology based on wafer bonding with vertical buried interconnections IEEE Trans El Dev 53 11 2006 2799 2808
4. Jung E, Neumann A, Wojakowski D, Ostmann A, Landsberger C, Aschenbrenner R, et al. Ultra thin chips for miniaturized products. In: Proc. 2002 electronics components and materials conference, ECTC, 2002, p. 1110-3.
5. K. Bock Polymer electronics systems - polytronics Proc. IEEE 93 8 2005 1400 1406
6. Burghartz JN, Graf H-G, Harendt C, Klingler H, Richter M, Strobel HDR. CMOS imager and their applications. In: Proc int conf on sol st. and integr circ tech; ICSICT, 2006, p. 528-31.
7. Burghartz JN, Engelhardt T, Graf H-G, Harendt C, Richter H, Scherjon C, et al. CMOS imager technologies for biomedical applications. In: Dig tech p int sol st circ conf; 2008, p. 142-3.
8. International technology roadmap for semiconductors (ITRS). < http://www.irs.net >.
9. J.D. Meindl, J.A. Davis, P. Zarkesh-Ha, C.S. Patel, K.P. Martin, and P.A. Kohl Interconnect opportunities for gigascale integration IBM J Res & Dev 46 2/3 2002 245 263
10. R.S. Patti Three-dimensional integrated circuits and the future of system-on-chip designs Proc IEEE 94 6 2006 1214 1224
11. B. Warnecke, M. Last, B. Liebowitz, and K.S.J. Pister Smart dust: communicating with a cubic millimeter Computer 34 2001 44 51
12. Landesberger C, Klink G, Schwinn G, Aschenbrenner R. New dicing and thinning concept improves mechanical reliability of ultra-thin silicon. In: Proc int symp adv pack mat; 2001, p. 92-7.
13. Swinnen B, Ruythooren W, DeMoor P, Bogaerts L, Carbonell L, De Munck K, et al. 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias. In: Techn dig int el dev mtg (IEDM); 2006. p. 371-80.
14. Dekker R. Sustrate transfer technology. PhD thesis, TU Delft, The Netherlands; 2 June 2004.
15. Zimmermann M, Burghartz JN, Appel W, Remmers N, Burwick C, Würz R et al. A seamless ultra-thin chip fabrication and assembly process. In: Techn dig int el dev mtg (IEDM); 2006. p. 1010-12.
16. J.N. Burghartz, W. Appel, H. Rempp, and M. Zimmermann A new fabrication and assembly process for ultra-thin chips IEEE Trans El Dev 56 2 2008 321 327
17. Heinze PM. Ultra-thin chips for 3D TSV's at ultra-low cost. In: 9th International workshop forum be-flexible, Munich; 2 December 2008.
18. Joyner JW, Zarkesh-Ha P, Meindl JD. A global interconnect design window for a three-dimensional system-on-a-chip. In: Proc int interconn tech conf (IITC); 2001. p. 154-6.
19. J.W. Joyner, P. Zarkesh-Ha, and J.D. Meindl Global interconnect design in a three-dimensional system-on-a-chip IEEE Trans Very Large Scal Integr Syst 12 4 2004 367 372
20. Lärmer F, Schilp A. German patent DE 4241045.
21. Liu F, Yu RR, Young AM, Doyle JP, Wang X, Shi L, et al. A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding. In: Techn dig int el dev mtg (IEDM); 2008. p. 1-4.
22. Rahman A, Trezza J, New B, Trimberger S. Die stacking technology for terabit chip-to-chip communications. In: Proc custom int circ cong (CICC); 2006. p. 587-90.
23. Ramm P, Wolf MJ, Klumpp A, Wieland R, Wunderle B, Michel B. Through silicon via technology -processes and reliability for wafer-level 3D system integration. In: Proc el comp techn conf (ECTC); 2008. p. 841-6.
24. H. Klauk, M. Halik, U. Zschieschang, F. Eder, D. Rohde, and G. Schmid Flexible organic complementary circuits IEEE Trans El Dev 52 4 2005 618 622
25. H. Klauk, D.J. Gundlach, and Th.N. Jackson Fast organic thin-film transistor circuits IEEE El Dev Lett 20 6 1999 289 291
26. S.K. Park, D.A. Mourey, S. Subramanian, J.E. Anthony, and Th.N. Jackson Polymeric substrate spin-cast OTFT circuits IEEE El Dev Lett 29 9 2008 1004 1006
27. H. Klauk, U. Zschieschang, and M. Halik Low-voltage organic thin-film transistors with large transconductance J Appl Phys 102 2007 074514-1 074514-2
28. H. Klauk, U. Zschieschang, J. Pflaum, and M. Halik Ultralow-power organic complementary circuits Nature 445 2007 745 748
29. M. Wu, X.-Z. Bo, J.C. Sturm, and S. Wagner Complementary metal-oxide-semiconductor thin film transistor circuits from a high temperature polycrystalline silicon process on steel foil substrates IEEE Trans El Dev 49 2002 1993 2000
30. Y.-D. Son, K.-D. Yang, B.-S. Bae, K.-Ch. Park, and J. Jang Dyanamic characteristics of MICC polycrystalline thin film transistors J Non-Cryst Solids 352 2006 1745 1748 (Pubitemid 43816545)
31. Y. Mishima, K. Yoshino, F. Takeuchi, K. Ohgata, M. Takei, and N. Sasaki High-performance CMOS circuits fabricated by excimer-laser-annealed poly-Si TFTs on glass substrates IEEE El Dev Lett 22 2 2001 89 91
32. Lärmer F, Schilp A. German patent DE 4241045.
33. A.A. Wereszczak, A.S. Barnes, K. Breder, and S. Binapal Probabilistic strength of {1 1 1} n-type silicon J Mater Sci: Mater El 11 2000 21 303
34. Zhao JH, Ebert E, Tellkamp J, Gupta V, Edwards D. Experimental evaluations of the strength of silicon die by 3-point bend vs. ball-on-ring tests. In: Proc IEEE 11th intersociety conference on thermal and thermomechanical phenomena in electronic systems; 2008. p. 687-94.
35. ASTM Standard C1239-07. Standard practise for reporting uniaxial strength data and estimating Weibull distribution parameters for advanced ceramics, ASTM International; 2007.
36. Ganesh WP, Lee C. Overview and emerging challenges in wafer thinning process for handheld applications. In: Proc int el maunf techn; 2006. p. 26.
37. S. Schoenfelder, E. Ebert, C. Landesberger, K. Bock, and J. Bagdahn Investigations of the influence of dicing techniques on the strength properties of thin silicon Microelectron Reliab 47 2007 168 178 (Pubitemid 46177065)
38. Rempp H, Burghartz J, Harendt C, Pricopi N, Pritschow M, Reuter C, et al. Ultra-thin chips on foil for flexible electronics. In: Dig tech p int sol st circ conf (ISSCC); 2008. p. 334-5.