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Volumn , Issue , 2001, Pages 154-156

A global interconnect design window for a three-dimensional system-on-a-chip

Author keywords

[No Author keywords available]

Indexed keywords


EID: 85001136347     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2001.930044     Document Type: Conference Paper
Times cited : (23)

References (10)
  • 1
    • 0034453365 scopus 로고    scopus 로고
    • Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology
    • K. W. Lee, et al., "Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology," Intl. Elec. Dev. Meeting (IEDM), 2000, pp. 165-168.
    • (2000) Intl. Elec. Dev. Meeting (IEDM) , pp. 165-168
    • Lee, K.W.1
  • 2
    • 0033903824 scopus 로고    scopus 로고
    • A Global Wiring Paradigm for Deep Submicron Design
    • Feb
    • D. Sylvester and K. Keutzer, "A Global Wiring Paradigm for Deep Submicron Design," IEEE Trans. CAD, vol. 19, no. 2, pp. 242-252, Feb. 2000.
    • (2000) IEEE Trans. CAD , vol.19 , Issue.2 , pp. 242-252
    • Sylvester, D.1    Keutzer, K.2
  • 5
    • 0033719714 scopus 로고    scopus 로고
    • An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC)
    • P. Zarkesh-Ha and J. D. Meindl, "An Integrated Architecture for Global Interconnects in a Gigascale System-on-a-Chip (GSoC)," Symp. VLSI Technology, 2000, pp. 194-195.
    • (2000) Symp. VLSI Technology , pp. 194-195
    • Zarkesh-Ha, P.1    Meindl, J.D.2
  • 7
    • 0034459340 scopus 로고    scopus 로고
    • Prediction of Net Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip
    • To be published Dec.
    • P. Zarkesh-Ha, J.A. Davis, and J.D. Meindl, "Prediction of Net Length Distribution for Global Interconnects in a Heterogeneous System-on-a-Chip," To be published IEEE Trans. VLSI Systems, Dec. 2000.
    • (2000) IEEE Trans. VLSI Systems
    • Zarkesh-Ha, P.1    Davis, J.A.2    Meindl, J.D.3
  • 8
    • 0034317044 scopus 로고    scopus 로고
    • Compact Distributed RLC Interconnect Models: Parts I and II
    • Nov
    • J. A. Davis and J. D. Meindl, "Compact Distributed RLC Interconnect Models: Parts I and II," IEEE Trans. Elec. Dev., vol. 47, no. 11, pp. 2068-2087, Nov. 2000.
    • (2000) IEEE Trans. Elec. Dev. , vol.47 , Issue.11 , pp. 2068-2087
    • Davis, J.A.1    Meindl, J.D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.