A new fabrication and assembly process for ultrathin chips

IEEE Transactions on Electron Devices

Volumn 56, Issue 2, 2009, Pages 321-327

  Burghartz, Joachim N ^a,b   Appel, Wolfgang ^a   Rempp, Horst D ^a   Zimmermann, Martin ^a  

^a Institut fur Mikroelektronik Stuttgart   (Germany)

^b UNIVERSITY OF STUTTGART   (Germany)

Author keywords

Cavities; CMOS FETs; CMOS integrated circuits (ICs); Conductivity; Electric field effects; Electrochemical processes; Electronics; Electrostatic processes; Etching; Flexible structures; IC fabrication; Manipulators; Microassembly; Micromachining; Semiconductor device doping; Semiconductor device manufacture; Semiconductor epitaxial layers; Separation; Silicon; Stress; Technology

Indexed keywords

ASSEMBLY; CMOS INTEGRATED CIRCUITS; COMPOSITE MICROMECHANICS; ELECTRIC CONDUCTIVITY; ELECTRIC FIELD EFFECTS; ELECTRIC FIELDS; ELECTROSTATICS; EPITAXIAL LAYERS; ETCHING; FABRICATION; FLEXIBLE STRUCTURES; INTEGRATED CIRCUITS; LUMPED PARAMETER NETWORKS; MACHINING; MANIPULATORS; MESFET DEVICES; MICROMACHINING; MOS CAPACITORS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR MATERIALS; SEMICONDUCTOR SWITCHES; SILICON WAFERS; STRESSES; SUBSTRATES;

CAVITIES; CMOS FETS; CMOS INTEGRATED CIRCUITS (ICS); CONDUCTIVITY; ELECTROCHEMICAL PROCESSES; ELECTRONICS; ELECTROSTATIC PROCESSES; IC FABRICATION; MICROASSEMBLY; SEMICONDUCTOR DEVICE DOPING; SEMICONDUCTOR EPITAXIAL LAYERS; SEPARATION; SILICON; STRESS; TECHNOLOGY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 59849109089     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2010581     Document Type: Article

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