-
1
-
-
21644452652
-
Dual stress liner for high performance sub- 45 nm gate length SOI CMOS manufacturing
-
H. S. Yang, R. Malik, S. Narasimha, Y. Li, R. Divakmi, P. Agnello, S. Allen, A. Antreasyan, J. C. Amold, K. Bandy, M. Belyansky, A. Bonnoit, G. Bronner, V. Chan, X. Chen, Z. Chen, D. Chidambarraa, A. Chou, W. Clark, S. W. Crowder, B. Engel, H. Harifuchi, S. F. Huang, R. Jagannathan, F. F. Jamin, Y. Kohyama, H. Kuroda, C. W. Lai, H. K. Lee, W.-H. Lee, E. H. Lim, W. Lai, A. Mallikarjunan, K. Matsumoto, A. McKnight, J. Nayak, H. Y. Ng, S. Panda, R. Rengarajan, M. Steigewalt, S. Subbanna, K. Subramanian, 1. Sudijono, G. Sudo, S.-P. Sun, B. Tessier, Y. Toyoshima, P. Tran, R.Wise, R.Wong, I. Y. Yang, C. H. Wann, and L. T. Su, "Dual stress liner for high performance sub- 45 nm gate length SOI CMOS manufacturing," in IEDM Tech. Dig., 2004, pp. 1075-1077.
-
(2004)
IEDM Tech. Dig.
, pp. 1075-1077
-
-
Yang, H.S.1
Malik, R.2
Narasimha, S.3
Li, Y.4
Divakmi, R.5
Agnello, P.6
Allen, S.7
Antreasyan, A.8
Amold, J.C.9
Bandy, K.10
Belyansky, M.11
Bonnoit, A.12
Bronner, G.13
Chan, V.14
Chen, X.15
Chen, Z.16
Chidambarraa, D.17
Chou, A.18
Clark, W.19
Crowder, S.W.20
Engel, B.21
Harifuchi, H.22
Huang, S.F.23
Jagannathan, R.24
Jamin, F.F.25
Kohyama, Y.26
Kuroda, H.27
Lai, C.W.28
Lee, H.K.29
Lee, W.-H.30
Lim, E.H.31
Lai, W.32
Mallikarjunan, A.33
Matsumoto, K.34
McKnight, A.35
Nayak, J.36
Ng, H.Y.37
Panda, S.38
Rengarajan, R.39
Steigewalt, M.40
Subbanna, S.41
Subramanian, K.42
Sudijono, I.43
Sudo, G.44
Sun, S.-P.45
Tessier, B.46
Toyoshima, Y.47
Tran, P.48
Wise, R.49
Wong, R.50
Yang, I.Y.51
Wann, C.H.52
Su, L.T.53
more..
-
2
-
-
33745148992
-
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell
-
E. Leobandung, H. Nayakama, D. Mocuta, K. Miyamoto, M. Angyal, H. V. Meer, K. McStay, I. Ahsan, S. Allen, A. Azuma, M. Belyansky, R.-V. Bentum, J. Cheng, D. Chidambarrao, B. Dirahoui, M. Fukasawa, M. Gerhardt, M. Gribelyuk, S. Halle, H. Harifuchi, D. Harmon, J. Heaps-Nelson, H. Hichri, K. Ida, M. Inohara, K. Inoue, K. Jenkins, T. Kawamura, B. Kim, S.-K. Ku, M. Kumar, S. Lane, L. Liebmann, R. Logan, I. Melville, K. Miyashita, A. Mocuta, P. O'Neil, M.-F. Ng, T. Nogami, A. Nomura, C. Norris, E. Nowak, M. Ono, S. Panda, C. Penny, C. Radens, R. Ramachandran, A. Ray, S.-H. Rhee, D. Ryan, T. Shinohara, G. Sudo, F. Sugaya, J. Strane, Y. Tan, L. Tsou, L. Wang, F. Wirbeleit, S. Wu, T. Yamashita, H. Yan, Q. Ye, D. Yoneyama, N. Zamdmer, H. Zhong, H. Zhu, W. Zhu, P. Agnello, S. Bukofsky, G. Bronner, E. Crabbé, G. Freeman, S.-F. Huang, T. Ivers, H. Kuroda, D. McHerron, J. Pellerin, Y. Toyoshima, S. Subbanna, N. Kepler, and L. Su, "High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell," in VLSI Symp. Tech. Dig., 2005, pp. 126-127.
-
(2005)
VLSI Symp. Tech. Dig.
, pp. 126-127
-
-
Leobandung, E.1
Nayakama, H.2
Mocuta, D.3
Miyamoto, K.4
Angyal, M.5
Meer, H.V.6
McStay, K.7
Ahsan, I.8
Allen, S.9
Azuma, A.10
Belyansky, M.11
Bentum, R.-V.12
Cheng, J.13
Chidambarrao, D.14
Dirahoui, B.15
Fukasawa, M.16
Gerhardt, M.17
Gribelyuk, M.18
Halle, S.19
Harifuchi, H.20
Harmon, D.21
Heaps-Nelson, J.22
Hichri, H.23
Ida, K.24
Inohara, M.25
Inoue, K.26
Jenkins, K.27
Kawamura, T.28
Kim, B.29
Ku, S.-K.30
Kumar, M.31
Lane, S.32
Liebmann, L.33
Logan, R.34
Melville, I.35
Miyashita, K.36
Mocuta, A.37
O'Neil, P.38
Ng, M.-F.39
Nogami, T.40
Nomura, A.41
Norris, C.42
Nowak, E.43
Ono, M.44
Panda, S.45
Penny, C.46
Radens, C.47
Ramachandran, R.48
Ray, A.49
Rhee, S.-H.50
Ryan, D.51
Shinohara, T.52
Sudo, G.53
Sugaya, F.54
Strane, J.55
Tan, Y.56
Tsou, L.57
Wang, L.58
Wirbeleit, F.59
Wu, S.60
Yamashita, T.61
Yan, H.62
Ye, Q.63
Yoneyama, D.64
Zamdmer, N.65
Zhong, H.66
Zhu, H.67
Zhu, W.68
Agnello, P.69
Bukofsky, S.70
Bronner, G.71
Crabbé, E.72
Freeman, G.73
Huang, S.-F.74
Ivers, T.75
Kuroda, H.76
McHerron, D.77
Pellerin, J.78
Toyoshima, Y.79
Subbanna, S.80
Kepler, N.81
Su, L.82
more..
-
3
-
-
46049096986
-
High performance 45-nm SOI technology with enhanced stress, porous low-k BEOL and immersion lithography
-
S. Narasimha, K. Onishi, H. M. Nayfeh, A. Waite, M. Weybright, J. Johnson, C. Fonseca, D. Corliss, C. Robinson, M. Crouse, D. Yang, C.-H. J. Wu, A. Gabor, T. Adam, I. Ahsan, M. Belyansky, L. Black, S. Butt, J. Cheng, A. Chou, G. Costrini, C. Dimitrakopoulos, A. Domenicucci, P. Fisher, A. Frye, S. Gates, S. Greco, S. Grunow, M. Hargrove, J. Holt, S.-J. Jeng, M. Kelling, B. Kim, W. Landers, G. Larosa, D. Lea, M. H. Lee, X. Liu, N. Lustig, A. McKnight, L. Nicholson, D. Nielsen, K. Nummy, V. Ontalus, C. Ouyang, X. Ouyang, C. Prindle, R. Pal, W. Rausch, D. Restaino, C. Sheraw, J. Sim, A. Simon, T. Standaert, C. Y. Sung, K. Tabakman, C. Tian, R. Van Den Nieuwenhuizen, H. Van Meer, A. Vayshenker, D. Wehella-Gamage, J. Werking, R. C. Wong, J. Yu, S. Wu, R. Augur, D. Brown, X. Chen, D. Edelstein, A. Grill, M. Khare, Y. Li, S. Luning, J. Norum, S. Sankaran, D. Schepis, R. Wachnik, R. Wise, C. Wann, T. Ivers, and P. Agnello, "High performance 45-nm SOI technology with enhanced stress, porous low-k BEOL and immersion lithography," in IEDM Tech. Dig., 2006, pp. 1-4.
-
(2006)
IEDM Tech. Dig.
, pp. 1-4
-
-
Narasimha, S.1
Onishi, K.2
Nayfeh, H.M.3
Waite, A.4
Weybright, M.5
Johnson, J.6
Fonseca, C.7
Corliss, D.8
Robinson, C.9
Crouse, M.10
Yang, D.11
Wu, C.-H.J.12
Gabor, A.13
Adam, T.14
Ahsan, I.15
Belyansky, M.16
Black, L.17
Butt, S.18
Cheng, J.19
Chou, A.20
Costrini, G.21
Dimitrakopoulos, C.22
Domenicucci, A.23
Fisher, P.24
Frye, A.25
Gates, S.26
Greco, S.27
Grunow, S.28
Hargrove, M.29
Holt, J.30
Jeng, S.-J.31
Kelling, M.32
Kim, B.33
Landers, W.34
Larosa, G.35
Lea, D.36
Lee, M.H.37
Liu, X.38
Lustig, N.39
McKnight, A.40
Nicholson, L.41
Nielsen, D.42
Nummy, K.43
Ontalus, V.44
Ouyang, C.45
Ouyang, X.46
Prindle, C.47
Pal, R.48
Rausch, W.49
Restaino, D.50
Sheraw, C.51
Sim, J.52
Simon, A.53
Standaert, T.54
Sung, C.Y.55
Tabakman, K.56
Tian, C.57
Nieuwenhuizen, R.58
Van Meer, H.59
Vayshenker, A.60
Wehella-Gamage, D.61
Werking, J.62
Wong, R.C.63
Yu, J.64
Wu, S.65
Augur, R.66
Brown, D.67
Chen, X.68
Edelstein, D.69
Grill, A.70
Khare, M.71
Li, Y.72
Luning, S.73
Norum, J.74
Sankaran, S.75
Schepis, D.76
Wachnik, R.77
Wise, R.78
Wann, C.79
Ivers, T.80
Agnello, P.81
more..
-
4
-
-
51949090508
-
45 nm high-k + metal gate strain-enhanced transistors
-
C. Auth, A. Cappellani, J.-S. Chun, A. Dalis, A. Davis, T. Ghani, G. Glass, T. Glassman, M. Harper, M. Hattendorf, P. Hentges, S. Jaloviar, S. Joshi, J. Klaus, K. Kuhn, D. Lavric, M. Lu, H. Mariappan, K. Mistry, B. Norris, N. Rahhal-orabi, P. Ranade, J. Sandford, L. Shifren, V. Souw, K. Tone, F. Tambwe, A. Thompson, D. Towner, T. Troeger, P. Vandervoorn, C. Wallace, J. Wiedemer, and C. Wiegand, "45 nm high-k + metal gate strain-enhanced transistors," in VLSI Symp. Tech. Dig., 2008, pp. 128-129.
-
(2008)
VLSI Symp. Tech. Dig.
, pp. 128-129
-
-
Auth, C.1
Cappellani, A.2
Chun, J.-S.3
Dalis, A.4
Davis, A.5
Ghani, T.6
Glass, G.7
Glassman, T.8
Harper, M.9
Hattendorf, M.10
Hentges, P.11
Jaloviar, S.12
Joshi, S.13
Klaus, J.14
Kuhn, K.15
Lavric, D.16
Lu, M.17
Mariappan, H.18
Mistry, K.19
Norris, B.20
Rahhal-Orabi, N.21
Ranade, P.22
Sandford, J.23
Shifren, L.24
Souw, V.25
Tone, K.26
Tambwe, F.27
Thompson, A.28
Towner, D.29
Troeger, T.30
Vandervoorn, P.31
Wallace, C.32
Wiedemer, J.33
Wiegand, C.34
more..
-
5
-
-
46049084627
-
A novel electrodeinduced strain engineering for high performance SOI FinFET utilizing Si (100) channel for both N and PMOSFETs
-
C. Y. Kang, R. Choi, S. C. Song, K. Choi, B. S. Ju, M. M. Hussain, B. H. Lee, G. Bersuker, C. Young, D. Heh, P. Kirsch, J. Barnet, J.-W. Yang, W. Xiong, H.-H. Tseng, and R. Jammy, "A novel electrodeinduced strain engineering for high performance SOI FinFET utilizing Si (100) channel for both N and PMOSFETs," in IEDM Tech. Dig., 2006, pp. 1-4.
-
(2006)
IEDM Tech. Dig.
, pp. 1-4
-
-
Kang, C.Y.1
Choi, R.2
Song, S.C.3
Choi, K.4
Ju, B.S.5
Hussain, M.M.6
Lee, B.H.7
Bersuker, G.8
Young, C.9
Heh, D.10
Kirsch, P.11
Barnet, J.12
Yang, J.-W.13
Xiong, W.14
Tseng, H.-H.15
Jammy, R.16
-
6
-
-
70549113315
-
High performance 32 nm SOI CMOS with high-k/ metal gate and 0.149 μm2 SRAM and ultra low-k back end with eleven levels of copper
-
B. Greene, Q. Liang, K. Amarnath, Y. Wang, J. Schaeffer, M. Cai, Y. Liang, S. Saroop, J. Cheng, A. Rotondaro, S-J. Han, R.Mo, K. McStay, S. Ku, R. Pala, M. Kumar, B. Dirahoui, B. Yang, F. Tamweber, W.-H. Lee, M. Steigerwalt, H. Weijtmans, J. Holt, L. Black, S. Samavedam, M. Turner, K. Ramani, D. Lee, M. Belyansky, M. Chowdhury, D. Aimé, B. Min, H. van Meer, H. Yin, K. Chan, M. Angyal, M. Zaleski, O. Ogunsola, C. Child, L. Zhuang, H. Yan, D. Permana, J. Sleight, D. Guo, S. Mittl, D. Ioannou, E. Wu, M. Chudzik, D.-G. Park, D. Brown, S. Luning, D. Mocuta, E. Maciejewski, K. Henson, and E. Leobandung, "High performance 32 nm SOI CMOS with high-k/ metal gate and 0.149 μm2 SRAM and ultra low-k back end with eleven levels of copper," in VLSI Symp. Tech. Dig., 2009, pp. 140-141.
-
(2009)
VLSI Symp. Tech. Dig.
, pp. 140-141
-
-
Greene, B.1
Liang, Q.2
Amarnath, K.3
Wang, Y.4
Schaeffer, J.5
Cai, M.6
Liang, Y.7
Saroop, S.8
Cheng, J.9
Rotondaro, A.10
Han, S.-J.11
Mo, R.12
McStay, K.13
Ku, S.14
Pala, R.15
Kumar, M.16
Dirahoui, B.17
Yang, B.18
Tamweber, F.19
Lee, W.-H.20
Steigerwalt, M.21
Weijtmans, H.22
Holt, J.23
Black, L.24
Samavedam, S.25
Turner, M.26
Ramani, K.27
Lee, D.28
Belyansky, M.29
Chowdhury, M.30
Aimé, D.31
Min, B.32
Van Meer, H.33
Yin, H.34
Chan, K.35
Angyal, M.36
Zaleski, M.37
Ogunsola, O.38
Child, C.39
Zhuang, L.40
Yan, H.41
Permana, D.42
Sleight, J.43
Guo, D.44
Mittl, S.45
Ioannou, D.46
Wu, E.47
Chudzik, M.48
Park, D.-G.49
Brown, D.50
Luning, S.51
Mocuta, D.52
MacIejewski, E.53
Henson, K.54
Leobandung, E.55
more..
-
7
-
-
64549106033
-
Gate length scaling and high drive currents enabled for high performance SOI technology using high-metal gate
-
K. Henson, H. Bu,M. H. Na, Y. Liang, U. Kwon, S. Krishnan, J. Schaeffer, R. Jha, N. Moumen, R. Carter, C. DeWan, R. Donaton, D. Guo, M. Hargrove, W. He, R. Mo, R. Ramachandran, K. Ramani, K. Schonenberg, Y. Tsang, X. Wang, M. Gribelyuk, W. Yan, J. Shepard, E. Cartier, M. Frank, E. Harley, R. Arndt, R. Knarr, T. Bailey, B. Zhang, K. Wong, T. Graves-Abe, E. Luckowski, D.-G. Park, V. Narayanan, M. Chudzik, and M. Khare, "Gate length scaling and high drive currents enabled for high performance SOI technology using high-metal gate," in IEDM Tech. Dig., 2008, pp. 645-648.
-
(2008)
IEDM Tech. Dig.
, pp. 645-648
-
-
Henson, K.1
Bu, H.2
Na, M.H.3
Liang, Y.4
Kwon, U.5
Krishnan, S.6
Schaeffer, J.7
Jha, R.8
Moumen, N.9
Carter, R.10
De Wan, C.11
Donaton, R.12
Guo, D.13
Hargrove, M.14
He, W.15
Mo, R.16
Ramachandran, R.17
Ramani, K.18
Schonenberg, K.19
Tsang, Y.20
Wang, X.21
Gribelyuk, M.22
Yan, W.23
Shepard, J.24
Cartier, E.25
Frank, M.26
Harley, E.27
Arndt, R.28
Knarr, R.29
Bailey, T.30
Zhang, B.31
Wong, K.32
Graves-Abe, T.33
Luckowski, E.34
Park, D.-G.35
Narayanan, V.36
Chudzik, M.37
Khare, M.38
more..
-
8
-
-
42949111167
-
Methods of producing plasma enhanced chemical vapor deposition silicon nitride thin films with high compressive and tensile stress
-
Apr.
-
M. Belyansky, M. Chace, O. Gluschenkov, J. Kempisty, N. Klymko, A. Madan, A. Mallikarjunan, S. Molis, P. Ronsheim, Y. Wang, D. Yang, and Y. Li, "Methods of producing plasma enhanced chemical vapor deposition silicon nitride thin films with high compressive and tensile stress," J. Vac. Sci. Technol. A, Vac. Surf. Films, vol.26, no.3, pp. 517-521, Apr. 2008.
-
(2008)
J. Vac. Sci. Technol. A, Vac. Surf. Films
, vol.26
, Issue.3
, pp. 517-521
-
-
Belyansky, M.1
Chace, M.2
Gluschenkov, O.3
Kempisty, J.4
Klymko, N.5
Madan, A.6
Mallikarjunan, A.7
Molis, S.8
Ronsheim, P.9
Wang, Y.10
Yang, D.11
Li, Y.12
-
9
-
-
0034452586
-
Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design
-
S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki, N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi, "Mechanical stress effect of etch-stop nitride and its impact on deep submicron transistor design," in IEDM Tech. Dig., 2000, pp. 247-250.
-
(2000)
IEDM Tech. Dig.
, pp. 247-250
-
-
Ito, S.1
Namba, H.2
Yamaguchi, K.3
Hirata, T.4
Ando, K.5
Koyama, S.6
Kuroki, S.7
Ikezawa, N.8
Suzuki, T.9
Saitoh, T.10
Horiuchi, T.11
-
10
-
-
0035715857
-
Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement
-
A. Shimizu, K. Hachimine, N. Ohki, H. Ohta, M. Koguchi, Y. Nonaka, H. Sato, and F. Ootsuka, "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement," in IEDM Tech. Dig., 2001, pp. 433-436.
-
(2001)
IEDM Tech. Dig.
, pp. 433-436
-
-
Shimizu, A.1
Hachimine, K.2
Ohki, N.3
Ohta, H.4
Koguchi, M.5
Nonaka, Y.6
Sato, H.7
Ootsuka, F.8
-
11
-
-
0036923355
-
The effective drive current in CMOS inverters
-
M. H. Na, E. J. Nowak, W. Haensch, and J. Cai, "The effective drive current in CMOS inverters," in IEDM Tech. Dig., 2002, pp. 121-124.
-
(2002)
IEDM Tech. Dig.
, pp. 121-124
-
-
Na, M.H.1
Nowak, E.J.2
Haensch, W.3
Cai, J.4
-
12
-
-
8344236776
-
A 90-nm logic technology featuring strained-silicon
-
Nov.
-
S. E. Thompson, M. Armstrong, C. Auth, M. Alavi, M. Buehler, R. Chau, S. Cea, T. Ghani, G. Glass, T. Hoffman, C.-H. Jan, C. Kenyon, J. Klaus, K. Kuhn, Z. Ma, B. Mcintyre, K. Mistry, A. Murthy, B. Obradovic, R. Nagisetty, P. Nguyen, S. Sivakumar, R. Shaheed, L. Shifren, B. Tufts, S. Tyagi, M. Bohr, and Y. El-Mansy, "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol.51, no.11, pp. 1790- 1797, Nov. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.11
, pp. 1790-1797
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Alavi, M.4
Buehler, M.5
Chau, R.6
Cea, S.7
Ghani, T.8
Glass, G.9
Hoffman, T.10
Jan, C.-H.11
Kenyon, C.12
Klaus, J.13
Kuhn, K.14
Maa, Z.15
McIntyre, B.16
Mistry, K.17
Murthy, A.18
Obradovic, B.19
Nagisetty, R.20
Nguyen, P.21
Sivakumar, S.22
Shaheed, R.23
Shifren, L.24
Tufts, B.25
Tyagi, S.26
Bohr, M.27
El-Mansy, Y.28
more..
-
13
-
-
0036928734
-
Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs
-
K. Rim, S. Narasimha, M. Longstreet, A. Mocuta, and J. Cai, "Low field mobility characteristics of sub-100 nm unstrained and strained Si MOSFETs," in IEDM Tech. Dig., 2002, pp. 43-44.
-
(2002)
IEDM Tech. Dig.
, pp. 43-44
-
-
Rim, K.1
Narasimha, S.2
Longstreet, M.3
Mocuta, A.4
Cai, J.5
-
14
-
-
8344266076
-
Comparison of thresholdvoltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs
-
Nov.
-
J. Lim, S. E. Thompson, and J. G. Fossum, "Comparison of thresholdvoltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs," IEEE Electron Device Lett., vol.25, no.11, pp. 731-733, Nov. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.11
, pp. 731-733
-
-
Lim, J.1
Thompson, S.E.2
Fossum, J.G.3
-
15
-
-
33646043420
-
Uniaxial-processinduced strained-Si: Extending the CMOS roadmap
-
May
-
S. E. Thompson, G. Sun, Y. Choi, and T. Nishida, "Uniaxial- processinduced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol.53, no.5, pp. 1010-1020, May 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.5
, pp. 1010-1020
-
-
Thompson, S.E.1
Sun, G.2
Choi, Y.3
Nishida, T.4
-
16
-
-
20544470957
-
Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain
-
Jun.
-
W. Zhao, A. Seabaugh, V. Adams, D. Jovanoic, and B.Winstead, "Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain," IEEE Electron Device Lett., vol.26, no.6, pp. 410- 412, Jun. 2005.
-
(2005)
IEEE Electron Device Lett.
, vol.26
, Issue.6
, pp. 410-412
-
-
Zhao, W.1
Seabaugh, A.2
Adams, V.3
Jovanoic, D.4
Winstead, B.5
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