High performance 32nm SOI CMOS with high-k/metal gate and 0.149μm 2 SRAM and ultra low-k back end with eleven levels of copper

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2009, Pages 140-141

  Greene, B ^a   Liang, Q ^a   Amarnath, K ^a   Wang, Y ^a   Schaeffer, J ^a   Cai, M ^a   Liang, Y ^a   Saroop, S ^a   Cheng, J ^a   Rotondaro, A ^a   Han, S J ^a   Mo, R ^a   McStay, K ^a   Ku, S ^a   Pal, R ^a   Kumar, M ^a   Dirahoui, B ^a   Yang, B ^a   Tamweber, F ^a   Lee, W H ^a   Steigerwalt, M ^a   Weijtmans, H ^a   Holt, J ^a   Black, L ^a   Samavedam, S ^a   Turner, M ^a   Ramani, K ^a   Lee, D ^a   Belyansky, M ^a   Chowdhury, M ^a   Aime D ^a   Min, B ^a   Van Meer, H ^a   Yin, H ^a   Chan, K ^a   Angyal, M ^a   Zaleski, M ^a   Ogunsola, O ^a   Child, C ^a   Zhuang, L ^a   Yan, H ^a   Permana, D ^a   Sleight, J ^a   Guo, D ^a   Mittl, S ^a   Ioannou, D ^a   Wu, E ^a   Chudzik, M ^a   Park, D G ^a   Brown, D ^a   Luning, S ^a   Mocuta, D ^a   Maciejewski, E ^a   Henson, K ^a   Leobandung, E ^a   more..

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

193NM IMMERSION LITHOGRAPHY; AC DRIVES; BULK SILICON; DUAL STRESS LINERS; GATE CAPACITANCE; GATE LENGTH; METAL GATE; PERFORMANCE BENEFITS; POWER PENALTY; SOI CMOS; SRAM CELL; STRAINED SILICON; TEST VEHICLE; ULTRA LOW-K;

CMOS INTEGRATED CIRCUITS;

STATIC RANDOM ACCESS STORAGE;

EID: 70549113315     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. M. Chudzik et al, VLSI Tech. Dig., 2007.
2. S. Narashimha et al, IEDM Tech. Digest, 2006.
3. K Henson et al, IEDM Tech. Digest, 2008.
4. H. Yang et al, IEDM Tech. Digest, 2008.