Designing and modeling for power integrity

IEEE Transactions on Electromagnetic Compatibility

Volumn 52, Issue 2, 2010, Pages 288-310

  Swaminathan, Madhavan ^a   Chung, Daehyun ^a   Grivet Talocia, Stefano ^b   Bharath, Krishna ^c   Laddha, Vishal ^d   Xie, Jianyong ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b POLITECNICO DI TORINO   (Italy)

^c INTEL CORPORATION   (United States)

^d NVIDIA   (United States)

Author keywords

Macro modeling; Passivity; Power distribution; Power integrity; Return path discontinuity; Signal integrity

Indexed keywords

DESIGN AND MODELING; DISCONTINUITY SIGNALS; FUTURE CHALLENGES; NONIDEAL; POWER DISTRIBUTIONS; POWER INTEGRITY; REFERENCE PLANE; SIMULTANEOUS SWITCHING NOISE; SUBSTRATE COUPLINGS; TEST VEHICLE; TIME-DOMAIN WAVEFORMS;

PASSIVATION; PRINTED CIRCUIT BOARDS; PRINTED CIRCUIT MANUFACTURE; PROBABILITY DISTRIBUTIONS; SIGNALING;

QUALITY ASSURANCE;

EID: 77953126489     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2010.2045382     Document Type: Article

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