Modeling of simultaneous switching noise in high speed systems

IEEE Transactions on Advanced Packaging

Volumn 24, Issue 2, 2001, Pages 132-142

  Chun, Sungjun ^a,b   Swaminathan, Madhavan ^a,b   Smith, Larry D ^a,c   Srinivasan, Jegannathan ^b   Jin, Zhang ^a,d   Iyer, Mahadevan K ^a,d  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c SUN MICROSYSTEMS   (United States)

^d INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Plane bounce; Plane modeling; Power distribution system; Resonator model; Return current; Simultaneous switching noise

Indexed keywords

SIMULTANEOUS SWITCHING NOISE (SNN);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER DISTRIBUTION; ELECTROMAGNETIC WAVES; MICROPROCESSOR CHIPS; SKIN EFFECT; SPURIOUS SIGNAL NOISE;

CMOS INTEGRATED CIRCUITS;

EID: 0035329204     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.928747     Document Type: Article

References (11)

1. Simultaneous switch noise and power plane bounce for CMOS technology
2. Modeling and transient simulation of planes in electronic packages
3. Reference plane parasitics modeling and their contribution to the power and ground path 'effective' inductance as seen by the output drivers
4. Power distribution modeling of high performance first level computer packages
5. Measurements, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA
6. Computation of the frequency response of multiple planes in gigahertz packages and boards
7. Computation and effect of field penetration through planes in multilayered package power distribution networks for giga-processors
8. Accurate power supply and ground plane pair models