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Volumn 2004-January, Issue January, 2004, Pages 2-7

Leakage Power Reduction by Dual-Vth Designs under Probabilistic Analysis of Vth Variation

Author keywords

Power minimization; variability; yield

Indexed keywords

DESIGN; OPTIMAL SYSTEMS; POWER ELECTRONICS;

EID: 84932168626     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2004.240694     Document Type: Conference Paper
Times cited : (8)

References (16)
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  • 3
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    • Jan
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    • Asenov, A.1    Kaya, S.2    Davies, J.H.3
  • 6
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    • Dual-threshold voltage assignment with transistor sizing for low power cmos circuits
    • P. Pant, R. Roy and A. Chatterjee, "Dual-Threshold Voltage Assignment with Transistor Sizing for Low Power CMOS Circuits," Trans, on VLSI, Vol. 9, No. 2, 4, 2001, 390-394.
    • (2001) Trans, on VLSI , vol.9 , Issue.2-4 , pp. 390-394
    • Pant, P.1    Roy, R.2    Chatterjee, A.3
  • 8
    • 0034878753 scopus 로고    scopus 로고
    • Design methodology and optimization strategy for dual-vth scheme using commercially available tools
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    • M. Hirabayashi, K. Nose, T. Sakurai, "Design methodology and optimization strategy for dual-VTH scheme using commercially available tools," ISLPED, pp. 283-286, Aug. 2001.
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    • Hirabayashi, M.1    Nose, K.2    Sakurai, T.3
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    • De, V.K.1    Tang, X.2    Meindl, J.D.3
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    • Alpha-power law mosfet model and its applications to cmos inverter delay and other formulas
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    • T. Sakurai, A.R. Newton, "Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas," IEEE Journal of Solid-State Circuits, Volume: 25 Issue: 2, pp. 584-594, April 1990.
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    • J.D. Warnock, et al., "The circuit and physical design of the POWER4 microprocessor," IBM J. of R&D, Vol. 46, pp. 27-52, Jan. 2002.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.