Transistor-specific delay modeling for SSTA

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2008, Pages 592-597

  Cline, Brian ^a   Chopra, Kaviraj ^a   Blaauw, David ^a   Torres, Andres ^a   Sundareswaran, Savithri ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CONCENTRATION (PROCESS); DATA STORAGE EQUIPMENT; DOPING (ADDITIVES); ELECTRIC BATTERIES; IMAGE SEGMENTATION; INDUSTRIAL ENGINEERING; LITHOGRAPHY; PROBABILITY DISTRIBUTIONS; STANDARDS; STATISTICAL METHODS; TESTING; TIME MEASUREMENT; TIMING DEVICES; TRANSISTORS;

CD MODELS; CD VARIATIONS; CONTEXT-DEPENDENT; CRITICAL DIMENSION; DEFOCUS; DELAY MODELING; DOPING CONCENTRATIONS; ERROR-PRONE; LINE-EDGE ROUGHNESS; RANDOM DOPANT FLUCTUATION; SOURCES OF VARIATION; SPATIAL CORRELATIONS; STANDARD CELLS; STANDARD DEVIATION; STATISTICAL TIMING; STATISTICAL TIMING TOOLS; TOTAL VARIATION; VARIATION MODELS;

PHOTORESISTS;

EID: 49749120178     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484741     Document Type: Conference Paper

References (13)

1. H. Chang and S.S. Sapatnekar, "Statistical Timing Analysis under Spatial Correlations," in IEEE Trans. on CAD, Vol. 24, Issue 9, pp. 1467-1482, Sept. 2005.
2. C. Visweswariah, et al., "First-Order Incremental Block-Based Statistical Timing Analysis," in IEEE Trans. on CAD, Vol. 25, Issue 10, pp. 2170-2180, Oct. 2006.
3. A. Agarwal, et al., "Statistical Delay Computation Considering Spatial Correlations," in Proc. of ASP-DAC, pp. 271-276, Jan. 2003.
4. H. Chang, et al., "Parameterized Block-based Statistical Timing Analysis with Non-Gaussian Parameters, Nonlinear Delay Functions," in Proc. of DAC, June 2005.
5. L. Zhang, et al., "Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model," in Proc. of DAC, pp. 83-88, June 2005.
6. K. Cao, J. Hu, S. Dobre, "Standard Cell Characterization Considering Lithography Induced Variations," in Proc. of DAC, pp. 801-804, July 2006.
7. P. Gupta, et al., "Modeling of Non-Uniform Device Geometries for Post-Lithography Circuit Analysis," in Proc. of SPIE, Vol. 6156, 61560U, March 2006.
8. M. Choi and L. Milor, "Impact on Circuit Performance of Deterministic Within-Die Variation in Nanoscale Semiconductor Manufacturing," in IEEE Trans. on CAD, Vol. 25, Issue 7, pp. 1350-1367, July 2006.
9. A. Pawloski, et al., "Line edge roughness and intrinsic bias for two methacrylate polymer resist systems," in J. Microlith., Microfab., Microsyst., Vol. 5, Issue 2, 023001, May 2006.
10. M. D. Stewart, et al., "Diffusion-induced line-edge roughness," in Proc. of SPIE, Vol. 5039, pp. 415-422, June 2003.
11. T. Yamaguchi and H. Namatsu, "Generation mechanism of surface roughness in resists: free volume effect on surface roughness," in Proc. of SPIE, Vol. 4690, pp. 921-928, July 2002.
12. I.T. Jolliffe, Principal Component Analysis, Springer Series in Statistics, New York, 1986.
13. Personal Communication with Andres Torres.