False path aware timing yield estimation under variability

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 161-166

  Xie, Lin ^a   Davoodi, Azadeh ^a   Saluja, Kewal K ^a   Sinkar, Abhishek ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; CIRCUIT TIMING; CRITICAL PATHS; DELAY MODELS; ENVIRONMENTAL VARIATIONS; FALSE PATHS; INPUT VECTOR; LOWER BOUNDS; MONTE CARLO; MULTIPLE INPUTS; PRIMARY INPUTS; SIMULATION RESULT; STATIC AND DYNAMIC; TIMING CONSTRAINTS; TIMING YIELD;

CELLULAR RADIO SYSTEMS; CONTROL THEORY; ESTIMATION; TIME MEASUREMENT;

TIMING CIRCUITS;

EID: 70350357187     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.17     Document Type: Conference Paper

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