Silicon nanowire transistors for implementing an field programmable gate array architecture with scan chain

Journal of Nanoelectronics and Optoelectronics

Volumn 4, Issue 3, 2009, Pages 342-352

  Bindal, Ahmet ^a   Ogura, Tomoko ^b   Ogura, Nori ^b   Hamedi Hagh, Sotoudeh ^a  

^a SAN JOSE STATE UNIVERSITY   (United States)

^b Halo LSI   (United States)

Author keywords

FPGA architecture; Low power; MOS transistor; Nanowire; Silicon nanowire

Indexed keywords

FPGA ARCHITECTURES; LOW POWER; MOS TRANSISTOR; MOS TRANSISTORS; SILICON NANOWIRES;

DATA FLOW ANALYSIS; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; NANOWIRES; SEMICONDUCTING SILICON; SMELTING; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

SPICE;

EID: 77952700887     PISSN: 1555130X     EISSN: None     Source Type: Journal    
DOI: 10.1166/jno.2009.1049     Document Type: Article

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