Silicon nanowire technology for applications in the field programmable gate array architectures

Journal of Nanoelectronics and Optoelectronics

Volumn 3, Issue 2, 2008, Pages 113-122

  Bindal, Ahmet ^a   Hamedi Hagh, Sotoudeh ^a   Ogura, Tomoko ^b  

^a SAN JOSE STATE UNIVERSITY   (United States)

^b Halo LSI   (United States)

Author keywords

FPGA; Nanotechnology; Nanowire; Silicon

Indexed keywords

ELECTRIC POWER UTILIZATION; ENERGY DISSIPATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; NANOWIRES; OPTICAL SENSORS; WORK FUNCTION;

BODY DIMENSIONS; CHANNEL LENGTHS; DEVICE DESIGNS; FAN OUTS; FPGA; IN BUILDINGS; LAYOUT AREAS; LOOK-UP TABLES; LOW-POWER; METAL WORK FUNCTIONS; NANOWIRE; OPTIMUM COMBINATIONS; POST-LAYOUT SIMULATIONS; POWER DISSIPATIONS; PROGRAMMABLE GATE ARRAYS; PROPAGATION DELAYS; SILICON NANOWIRE TECHNOLOGIES; SILICON NANOWIRE TRANSISTORS; SINGLE TRANSISTORS; TRANSIENT PERFORMANCE; TRANSIENT RESPONSE;

NANOTECHNOLOGY;

EID: 62549090123     PISSN: 1555130X     EISSN: None     Source Type: Journal    
DOI: 10.1166/jno.2008.205     Document Type: Review

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