Quasi-resonant interconnects: A low power, low latency design methodology

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 2, 2009, Pages 181-193

  Rosenfeld, Jonathan ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

Latency; On chip inductors; On chip interconnects; Power dissipation; Resonance

Indexed keywords

ARSENIC; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC INDUCTORS; INTERCONNECTION NETWORKS; OPTICAL INTERCONNECTS; RESONANCE;

ANALYSIS AND DESIGNS; ANALYSIS GUIDELINES; CMOS TECHNOLOGIES; DATA SIGNALS; DESIGN METHODOLOGIES; DISTRIBUTED MODELS; INTERCONNECT NETWORKS; LATENCY; LOW LATENCIES; LOW-POWER; ON-CHIP INDUCTORS; ON-CHIP INTERCONNECT; ON-CHIP INTERCONNECTS; POWER CONSUMPTION; POWER DISSIPATION; POWER-DELAY PRODUCTS; REPEATER INSERTIONS;

ELECTRIC POWER UTILIZATION;

EID: 58849135768     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2011197     Document Type: Article

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