Variation-aware speed binning of multi-core processors

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 307-314

  Sartori, John ^a   Pant, Aashish ^b   Kumar, Rakesh ^a   Gupta, Puneet ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Binning; Multi core; Performance; Process variations

Indexed keywords

CORE PROCESSORS; DIFFERENT PROCESS; MANUFACTURING VARIATION; MAXIMUM OPERATING FREQUENCY; MULTI CORE; MULTI-CORE PROCESSOR; NON-TRIVIAL TASKS; PROCESS VARIATION; SPEED BINNING; VARIATION MODELS;

CURVE FITTING; NANOTECHNOLOGY;

MICROPROCESSOR CHIPS;

EID: 77952656638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450442     Document Type: Conference Paper

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