Distributed peak power management for many-core architectures

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2009, Pages 1556-1559

  Sartori, John ^a   Kumar, Rakesh ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUDGET CONTROL; DECISION MAKING; POWER MANAGEMENT;

CENTRALIZED DECISION MAKING; CORRECTIVE ACTIONS; EXPONENTIAL EXPLOSION; GRADIENT ASCENT; INSTANTANEOUS POWER; MANY-CORE ARCHITECTURE; PEAK POWER; POWER BUDGETS;

COMPUTER ARCHITECTURE;

EID: 70350057333     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090910     Document Type: Conference Paper

References (8)

1. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In ISCA '00: Proceedings of the 27th annual international symposium on Computer architecture, pages 83.94, 2000.
2. D. M. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva, A. Buyuktosunoglu, J.-D. Wellman, V. Zyuban, M. Gupta, and P. W. Cook. Power-aware microarchitecture: Design and modeling challenges for next-generation microprocessors. IEEE Micro, 20(6):26.44, 2000.
3. Intel Corp. Intel's Teraflops Research Chip.
4. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An analysis of efficient multi-core global power management policies: Maximizing performance for a given power budget. In MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, 2006.
5. R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas. Single-ISA Heterogeneous Multi-core Architectures for MultithreadedWorkload Performance. In International Symposium on Computer Architecture, June 2004.
6. T. Sherwood, E. Perelman, G. Hamerly, S. Sair, and B. Calder. Discovering and exploiting program phases. In IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, Dec. 2003.
7. A. Snavely and D. Tullsen. Symbiotic jobscheduling for a simultaneous multithreading architecture. In Eighth International Conference on Architectural Support for Programming Languages and Operating Systems, Nov. 2000.
8. D. Tullsen. Simulation and modeling of a simultaneous multithreading processor. In 22nd Annual Computer Measurement Group Conference, Dec. 1996.