-
1
-
-
33748848240
-
-
H., Intel Corporation, Tech. Rep., Mar.
-
S. Y. Borkar, P. Dubey, K. C. Kahn, D. J. Kuck, H., "Platform 2015: Intel processor and platform evolution for the next decade", Intel Corporation, Tech. Rep., Mar. 2005
-
(2005)
Platform 2015: Intel Processor and Platform Evolution for the next Decade
-
-
Borkar, S.Y.1
Dubey, P.2
Kahn, K.C.3
Kuck, D.J.4
-
2
-
-
0036046921
-
Power estimation in global interconnects and its reduction using a novel repeater optimization methodology
-
P. Kapur, G. Chandra, K. C. Saraswat, "Power estimation in global interconnects and its reduction using a novel repeater optimization methodology", Design Automation Conference, 2002
-
Design Automation Conference, 2002
-
-
Kapur, P.1
Chandra, G.2
Saraswat, K.C.3
-
3
-
-
84886735141
-
Interconnect and thermal-aware floorplanning for 3D microprocessors
-
W.-L. Hung, G. M. Link, Y.Xie, N. Vijaykrishnan, M. J. Irwin, "Interconnect and thermal-aware floorplanning for 3D microprocessors", International Symposium on Quality of Electronic Design, Mar. 2006.
-
International Symposium on Quality of Electronic Design, Mar. 2006
-
-
Hung, W.-L.1
Link, G.M.2
Xie, Y.3
Vijaykrishnan, N.4
Irwin, M.J.5
-
4
-
-
33748533457
-
Three-dimensional integrated circuits
-
W. Topol, D.C. La Tulipe Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K.W. Guarini, M. Leong, "Three-dimensional integrated circuits", IBM J. Research and Development, vol. 4, 2006.
-
(2006)
IBM J. Research and Development
, vol.4
-
-
Topol, W.1
La Tulipe Jr., D.C.2
Shi, L.3
Frank, D.J.4
Bernstein, K.5
Steen, S.E.6
Kumar, A.7
Singco, G.U.8
Young, A.M.9
Guarini, K.W.10
Leong, M.11
-
5
-
-
40349090128
-
Die stacking (3d) microarchitecture
-
B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, C. Webb, "Die stacking (3d) microarchitecture", International. Symposium on Microarchitecture, Dec. 2006, pp.
-
International. Symposium on Microarchitecture, Dec. 2006
-
-
Black, B.1
Annavaram, M.2
Brekelbaum, N.3
DeVale, J.4
Jiang, L.5
Loh, G.H.6
McCaule, D.7
Morrow, P.8
Nelson, D.W.9
Pantuso, D.10
Reed, P.11
Rupley, J.12
Shankar, S.13
Shen, J.14
Webb, C.15
-
6
-
-
0032592096
-
Design Challenges of Technology Scaling
-
S. Borkar, "Design Challenges of Technology Scaling", IEEE Micro, 19(4), 1999.
-
(1999)
IEEE Micro
, vol.19
, Issue.4
-
-
Borkar, S.1
-
7
-
-
0003815341
-
Managing the Impact of Increasing Microprocessor Power Consumption
-
S. Gunther, F. Binns, D. M. Carmean, J. C. Hall, "Managing the Impact of Increasing Microprocessor Power Consumption", Intel Technology Journal, 2001
-
(2001)
Intel Technology Journal
-
-
Gunther, S.1
Binns, F.2
Carmean, D.M.3
Hall, J.C.4
-
9
-
-
56849130292
-
Full-chip leakage current estimation based on statistical sampling techniques
-
S. Liu, et al, "Full-chip leakage current estimation based on statistical sampling techniques," in Proc of GLSVLSI, 2008
-
Proc of GLSVLSI, 2008
-
-
Liu, S.1
-
10
-
-
57649094597
-
A probabilistic technique for full-chip leakage estimation
-
S. Liu, et al, "A probabilistic technique for full-chip leakage estimation, " in Proc of ISLPED, 2008
-
Proc of ISLPED, 2008
-
-
Liu, S.1
-
11
-
-
1542269365
-
Statistical estimation of leakage current considering inter- And intra-die process variation
-
R. Rao, A. Srivastava, D. Blaauw, D. Sylvester "Statistical estimation of leakage current considering inter- and intra-die process variation", International Symposium on Low Power Electronics and Design, 2003.
-
International Symposium on Low Power Electronics and Design, 2003
-
-
Rao, R.1
Srivastava, A.2
Blaauw, D.3
Sylvester, D.4
-
12
-
-
0242335116
-
Thermally driven reliability issues in microelectronic systems: Status-quo and challenges
-
C. J. Lasance, "Thermally driven reliability issues in microelectronic systems: status-quo and challenges", Microelectronics Reliability, 2003.
-
(2003)
Microelectronics Reliability
-
-
Lasance, C.J.1
-
14
-
-
34547143358
-
HybDTM: A Coordinated Hardware-Software Approach for Dynamic Thermal Management
-
A. Kumar, L. Shang, L. S. Peh, N. K. Jha, "HybDTM: A Coordinated Hardware-Software Approach for Dynamic Thermal Management," Design Automation Conference, 2006.
-
Design Automation Conference, 2006
-
-
Kumar, A.1
Shang, L.2
Peh, L.S.3
Jha, N.K.4
-
16
-
-
16244385917
-
A thermal-driven floorplanning algorithm for 3D ICs
-
J. Cong, J. Wei, and Y. Zhang, "A thermal-driven floorplanning algorithm for 3D ICs", International Conference on. Computer-Aided Design, 2004,
-
International Conference On. Computer-Aided Design, 2004
-
-
Cong, J.1
Wei, J.2
Zhang, Y.3
-
19
-
-
47849132667
-
Three-dimensional chip-multiprocessor run-time thermal management
-
C. Zhu, C. Zhu; Z. Gu, L. Shang, R.P. Dick, R. Joseph, "Three-dimensional chip-multiprocessor run-time thermal management", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008.
-
(2008)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
-
-
Zhu, C.1
Zhu, C.2
Gu, Z.3
Shang, L.4
Dick, R.P.5
Joseph, R.6
-
21
-
-
70350055176
-
Dynamic Thermal Management in 3D Multicore Architectures
-
Apr.
-
A. K. Coskun, J. L. Ayala, D. Atienza, T. Simunic, Y. Leblebici, "Dynamic Thermal Management in 3D Multicore Architectures", Design, Automation & Test in Europe, Apr. 2009.
-
(2009)
Design, Automation & Test in Europe
-
-
Coskun, A.K.1
Ayala, J.L.2
Atienza, D.3
Simunic, T.4
Leblebici, Y.5
-
22
-
-
55949114476
-
Thermal Management for 3D Processors via Task Scheduling
-
X. Zhou, Y. Xu, Y. Du, Y. Zhang, J. Yang , " Thermal Management for 3D Processors via Task Scheduling", International Conference on Parallel Processing, Sep. 2008:
-
International Conference on Parallel Processing, Sep. 2008
-
-
Zhou, X.1
Xu, Y.2
Du, Y.3
Zhang, Y.4
Yang, J.5
-
23
-
-
85009352442
-
Temperature-aware microarchitecture: Modeling and implementation
-
K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy, D. Tarjan, "Temperature-aware microarchitecture: Modeling and implementation", ACM Transactions on Architecture and Code Optimization, 2004
-
(2004)
ACM Transactions on Architecture and Code Optimization
-
-
Skadron, K.1
Stan, M.R.2
Sankaranarayanan, K.3
Huang, W.4
Velusamy, S.5
Tarjan, D.6
-
24
-
-
0033323845
-
A physical alpha-power law MOSFET model
-
Oct.
-
K. A. Bowman, B. L. Austin, J.C. Eble, X. Tang, J. D. Meindl, "A physical alpha-power law MOSFET model", IEEE J. Solid-State Circuits, vol. 34, Oct. 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
-
-
Bowman, K.A.1
Austin, B.L.2
Eble, J.C.3
Tang, X.4
Meindl, J.D.5
-
25
-
-
33846535493
-
The M5 simulator: Modeling networked systems
-
N. L. Binkert, R.G. Dreslinski, L.R. Hsu, K. T. Lim, A. G.. Saidi, and S. K. Reinhardt, "The M5 simulator: Modeling networked systems", Proc. IEEE Micro Special issue on Architecture Simulation and Modeling, Jul. 2006
-
Proc. IEEE Micro Special Issue on Architecture Simulation and Modeling, Jul. 2006
-
-
Binkert, N.L.1
Dreslinski, R.G.2
Hsu, L.R.3
Lim, K.T.4
Saidi, A.G.5
Reinhardt, S.K.6
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