Spice-accurate SystemC macromodels of noisy on-chip communication channels

Proceedings - 11th IEEE Workshop on Signal Propagation on Interconnects, SPI 2007

Volumn , Issue , 2007, Pages 11-14

  Terrassan, Nicola ^a   Bertozzi, Davide ^a   Bogliolo, Alessandro ^b  

^a UNIVERSITY OF FERRARA   (Italy)

^b UNIVERSITY OF URBINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION ABSTRACTION; CONVENTIONAL CIRCUITS; HDL SIMULATION; HIGH-SPEED INTERCONNECTS; INTERCONNECT ANALYSIS; MACRO-MODELS; NANOSCALE TECHNOLOGIES; NOISE EFFECTS; ON-CHIP COMMUNICATION CHANNELS; PERFORMANCE ESTIMATION; PHYSICAL CHANNELS; POWER BUDGETS; SYSTEM DESIGNERS; SYSTEMC;

COMMUNICATION CHANNELS (INFORMATION THEORY); INTERCHANGES; NANOTECHNOLOGY; RELIABILITY ANALYSIS; TECHNICAL PRESENTATIONS;

SPICE;

EID: 77950681689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPI.2007.4512195     Document Type: Conference Paper

References (14)

1. D. Bertozzi, L. Benini, B. Ricco', "Parametric timing and power macromodels for high level simulation of low-swing interconnects", Int. Symp. on Low Power Electronics and Design, 2002.
2. Xiangyuan Liu, Shuming Chen, "Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning", Proceedings of the 16th ACM Great Lakes symposium on VLSI, pp.91-94, 2006. (Pubitemid 44729224)
3. Sylvester, D.,Chenming Hu, "Analytical modeling and characterization of deep-submicrometer interconnect", Proceedings of the IEEE, Vol.89 , Issue 5, pp.634-664, 2005. (Pubitemid 33769117)
4. J. Xi, Z. Huang, P. Zhong, "Energy macro-modeling of embedded microprocessor using SystemC", Int. Conf. on Electro/Information Technology, 6 pp., 2005.
5. Lundgren, J. Ytterdal, T. Vonbun, K. O'Nils, M., "Taking mixed- signal substrate noise coupling simulation to the behavioral level using SystemC", Int. Workshop on System-on-Chip for Real-Time Applications, pp.201-205, 2004.
6. S. Niar, S. Meftali, J. L. Dekeyser, "Power consumption awareness in cache memory design with SystemC", Int. Conference on Microelectronics, pp.244-247, 2004. (Pubitemid 40927769)
7. J. Xi, P. Zhong, "A system-level network-on-chip simulation framework with analytical interconnecting wire models", Int. Conf. on Electro/Information Technology, pp. 301-306, 2006. (Pubitemid 46970124)
8. Berkeley Predictive Technology Models, http://www.eas.asu.edu/ptm/
9. F. Angiolini, P. Meloni, S. Carta, L. Benini, L. Raffo, "Contrasting a NoC and a traditional interconnect fabric with layout awareness", DATE 2006, pp. 124-129.
10. Rung-Bin Lin, "Coupling reduction analysis of bus-invert coding", ISCAS2005, pp. 5862-5865, Vol. 6.
11. H. Zhang, V. George, Jan M. Rabaey, "Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness", in IEEE Trans. VLSI Systems, pp. 264-272, 2000.
12. T. Dumitra, S. Kerner, R. Marculescu, "Towards on-chip fault-tolerant communication", in Proceedings of the 2003 conference on Asia South Pacific design automation, pp. 225-232, 2003.
13. A. Bogliolo, and P. Olivo, "Dealing with noise margins in highspeed voltage-mode signaling," in Proc. of IEEE Workshop on Signal Propagation on Interconnects, pp. 133-134, 2002.
14. A. Ghadiri, H. Mahmoodi, "Dual-Edge Triggered Static Pulsed Flip-Flops", in Int. Conf. on VLSI Design, pp. 846-849, 2005. (Pubitemid 41675376)