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Volumn 2006, Issue , 2006, Pages 91-94

Delay and power estimation models of low-swing interconnects for design planning

Author keywords

Delay; Estimation model; Low swing interconnect; Power

Indexed keywords

COMPUTER SIMULATION; LOGIC DESIGN; PARAMETER ESTIMATION; SYSTEMS ANALYSIS;

EID: 33750925164     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1127908.1127932     Document Type: Conference Paper
Times cited : (2)

References (7)
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    • Banerjee, K., and Mehrotra, A. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Trans. on Electron Devices, 49, 11 (2002), 2001-2007.
    • (2002) IEEE Trans. on Electron Devices , vol.49 , Issue.11 , pp. 2001-2007
    • Banerjee, K.1    Mehrotra, A.2
  • 2
    • 0031705061 scopus 로고    scopus 로고
    • EWA: Efficient wiring-sizing algorithm for signal nets and clock nets
    • Kay, R., and Pileggi, L. T. EWA: efficient wiring-sizing algorithm for signal nets and clock nets. IEEE Trans. on CAD, 17, 1 (1998), 40-49.
    • (1998) IEEE Trans. on CAD , vol.17 , Issue.1 , pp. 40-49
    • Kay, R.1    Pileggi, L.T.2
  • 3
    • 0141698475 scopus 로고    scopus 로고
    • A single-chip terabit switch
    • Palo Alto, USA
    • Dally, W. A single-chip terabit switch. In Proc. of Hot Chips 13. (Palo Alto, USA, 2001). 19-21.
    • (2001) Proc. of Hot Chips , vol.13 , pp. 19-21
    • Dally, W.1
  • 4
    • 33847298641 scopus 로고    scopus 로고
    • Interconnect Delay Optimization Using a Novel Hybrid Insertion Strategy
    • Shanghai, China
    • Liu, X. Y., and Chen, S. M. Interconnect Delay Optimization Using a Novel Hybrid Insertion Strategy. In Proc. of ASICON'05. (Shanghai, China, 2005). 772-775.
    • (2005) Proc. of ASICON'05 , pp. 772-775
    • Liu, X.Y.1    Chen, S.M.2
  • 5
    • 0035368267 scopus 로고    scopus 로고
    • Interconnect performance estimation models for design planning
    • Cong, J., and Pan, Z. D. Interconnect performance estimation models for design planning. IEEE Trans. on CAD of ICs and Systems, 20, 6 (2001), 739-752.
    • (2001) IEEE Trans. on CAD of ICs and Systems , vol.20 , Issue.6 , pp. 739-752
    • Cong, J.1    Pan, Z.D.2
  • 6
    • 0348040034 scopus 로고    scopus 로고
    • A high-level interconnect power model for design space exploration
    • San Jose, CA
    • Gupta, P., Zhong, L., and Jha, N. K. A high-level interconnect power model for design space exploration. In Proc. of ICCAD'03. (San Jose, CA, 2003). 551-558.
    • (2003) Proc. of ICCAD'03 , pp. 551-558
    • Gupta, P.1    Zhong, L.2    Jha, N.K.3
  • 7
    • 0036949332 scopus 로고    scopus 로고
    • Parametric timing and power macromodels for high level simulation of low-swing interconnects
    • Monterey, CA
    • Bertozzi, D., Benini, L., and Ricco, B. Parametric timing and power macromodels for high level simulation of low-swing interconnects. In Proc. of ISLPED'2002. (Monterey, CA, 2002). 308-312.
    • (2002) Proc. of ISLPED'2002 , pp. 308-312
    • Bertozzi, D.1    Benini, L.2    Ricco, B.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.