Power consumption awareness in cache memory design with SystemC

Proceedings of the International Conference on Microelectronics, ICM

Volumn , Issue , 2004, Pages 244-247

  Niar, Smail ^a,b   Meftali, Samy ^a   Dekeyser, Jean Luc ^a  

^a UNIV LILLE   (France)

^b UNIVERSITÉ DE VALENCIENNES   (France)

Author keywords

Cache; Power consumption; Processor; SystemC

Indexed keywords

C (PROGRAMMING LANGUAGE); COMPUTER HARDWARE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; EMBEDDED SYSTEMS; ENERGY UTILIZATION; IMAGE PROCESSING; MATHEMATICAL MODELS; PROGRAM PROCESSORS; TELECOMMUNICATION;

CACHE; POWER CONSUMPTION; PROCESSORS; REGISTER TRANSFER LEVEL (RTL); SYSTEM ON CHIP (SOC) TECHNOLOGY; SYSTEMC;

CACHE MEMORY;

EID: 21644484172     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. T. Mudge. "Power: A first class design constraint", IEEE Computer,April 2001.
2. G.Martin H.Chang, "Winning the SoC Revolution", Kluwer Academic Publi.
3. www.systemc.org
4. www.microlib.org
5. Orinoco, www.chipvision.com
6. S. Wilton and N. Jouppi. An Enhanced Access and Cycle Time Model for On-Chip Caches. Research Report WRL 1994.
7. P. Shivakumar and N. P. Jouppi. CACTI 3.0: An integrated cache timing, power, and area model, Research Report WRL01.
8. S. Niar, L.Eekhout, K.DeBosschere, "Comparing multiported cache schemes". Inter. Conf. on Parallel and Distributed Processing Techniques and Appli., 2003.