Dealing with noise margins in high-speed voltage-mode signaling

Proceedings - 6th IEEE Workshop on Signal Propagation on Interconnects, SPI

Volumn , Issue , 2002, Pages 133-134

  Bogliolo, Alessandro ^a   Olivo, Piero ^b  

^a UNIVERSITY OF URBINO   (Italy)

^b UNIVERSITY OF FERRARA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BIT RATE (BPP); CMOS BUFFERS; HIGH SPEEDS; NOISE MARGIN (NM); ON-CHIP SIGNALING; SCHMITT TRIGGERS; SIGNAL PROPAGATION; VOLTAGE-MODE (VM);

CRACK PROPAGATION; SIGNAL PROCESSING;

INTERCHANGES;

EID: 46649114169     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPI.2002.258297     Document Type: Conference Paper

References (2)

1. Caignet, F., Delmas-Bendhia, S., and Sicard, E., "The challenge of signal integrity in deep-submicrometer CMOS technology," IEEE iProceedings, Vol. 88, No. 4 (2001), pp. 556-573.
2. Baker, R. J., Boyce, D. E., and Li, H. W., CMOS Circuit Design, Layout and Simulation, Wiley-IEEE Press (1998).