Parametric timing and power macromodels for high level simulation of low-swing interconnects

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 307-312

  Bertozzi, Davide ^a   Benini, Luca ^a   Ricco, Bruno ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Delay; Interconnect; Low swing; Macromodel; Power

Indexed keywords

COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER SIMULATION; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; SCHEMATIC DIAGRAMS; SIGNAL RECEIVERS; VLSI CIRCUITS;

BACK ANNOTATION TECHNIQUE; HIGH LEVEL SIMULATION; LOW SWING INTERCONNECTS; PARAMETRIC TIMING; POWER CONSUMPTION; POWER MACROMODELS; REGISTER TRANSFER LEVEL;

INTERCONNECTION NETWORKS;

EID: 0036949332     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146760     Document Type: Conference Paper

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