III-V/Ge channel engineering for future CMOS

ECS Transactions

Volumn 19, Issue 5, 2009, Pages 361-372

  Wistey, M A ^a   Singisetti, U ^a   Burek, G J ^a   Kim, E ^b   Thibeault, B J ^a   Nelson, A ^a   Cagnon, J ^a   Lee, Y J ^c   Bank, S R ^d   Stemmer, S ^a   McIntyre, P C ^b   Gossard, A C ^a   Rodwell, M J W ^a  

^a University of California   (United States)

^b STANFORD UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

^d UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEGREES OF FREEDOM (MECHANICS); GALLIUM ALLOYS; GALLIUM COMPOUNDS; INDIUM ALLOYS; MOSFET DEVICES; SEMICONDUCTING INDIUM; SEMICONDUCTING INDIUM GALLIUM ARSENIDE; SEMICONDUCTOR ALLOYS; SILICON;

ACCESS RESISTANCE; ALTERNATIVE MATERIALS; CHANNEL ENGINEERING; CONTACT RESISTIVITIES; DIELECTRIC THICKNESS; PARASITIC RESISTANCES; PEAK TRANSCONDUCTANCE; SOURCE-DRAIN REGROWTHS;

CMOS INTEGRATED CIRCUITS;

EID: 77149151903     PISSN: 19385862     EISSN: 19386737     Source Type: Conference Proceeding    
DOI: 10.1149/1.3119559     Document Type: Conference Paper

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