Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 211-214

  Stojanovic, Vladimir ^a   Markovic, Dejan ^b   Nikolic, Borivoje ^b   Horowitz, Mark A ^a   Brodersen, Robert W ^b  

^a STANFORD UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL LOGIC; DELAY CONSTRAINTS; DELAY MODELING; ENERGY PROFILE; ENERGY-DELAY TRADEOFFS; MULTIPLE SUPPLIES; PEAK PERFORMANCE; SUPPLY VOLTAGES;

ELECTRIC NETWORK TOPOLOGY; ENERGY CONSERVATION; ENERGY UTILIZATION; GATES (TRANSISTOR);

OPTIMIZATION;

EID: 3843135512     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. A.P. Chandrakasan and R.W. Brodersen, "Minimizing Power Consumption in Digital CMOS Circuits," in Proc. IEEE, pp. 498-522, Apr. 1995.
2. T. Sakurai and R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE JSSC, pp. 584-594, Apr. 1990.
3. I. Sutherland, B. Sproul, and D. Harris, "Logical Effort: Designing Fast CMOS Circuits," San Francisco, CA: Morgan Kaufmann, 1999.
4. S. Ma and P. Franzon, "Energy Control and Accurate Delay Estimation in the Design of CMOS Buffers," IEEE JSSC, pp. 1150-1153, Sept. 1994.
5. J-M. Shyu et al., "Optimization-Based Transistor Sizing," IEEE JSSC, pp. 400-409, April 1988.
6. B.S. Amrutur "Design and Analysis of Fast Low-Power SRAMs," Ph. D. dissertation, Stanford Univ., Aug. 1999.