An embedded processor core for consumer appliances with 2.8GFLOPS and 36M polygons/s FPU

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Arakawa, Fumio ^a   Yoshinaga, Takeshi ^b   Hayashi, Tomoichi ^b   Kiyoshige, Yoshikazu ^b   Okada, Takashi ^a   Nishibori, Masakazu ^c   Hiraoka, Toru ^b   Ozawa, Motokazu ^a   Kodama, Tomoyuki ^a   Irita, Takahiro ^c   Kamei, Tatsuya ^c   Ishikawa, Makoto ^a   Nitta, Yusuke ^c   Nishii, Osamu ^b   Hattori, Toshihiro ^b  

^a Hitachi ^*  (Japan)

^b SuperH (Japan)   (Japan)

^c RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CARRY PROPAGATE ADDER (CPA); CONSUMER APPLIANCES; EMBEDDED PROCESSOR CORE; LEADING NON-ZERO (LNZ) DETECTOR;

COMPUTER GRAPHICS; CONSUMER PRODUCTS; DATA PROCESSING; DIGITAL ARITHMETIC; HARDWARE; NETWORKS (CIRCUITS); PERSONAL COMPUTERS; STORAGE ALLOCATION (COMPUTER);

PROGRAM PROCESSORS;

EID: 2442646663     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. T. Yamada et al., "A 133MHz 170mW 10μA Standby Application Processor for 3G Cellular Phones," ISSCC Dig. Tech. Papers, pp. 370-371, 474, 2002.
2. K. Kutaragi et al., "A Microprocessor with a 128b CPU, 10 Floating-point MACs, 4 Floating-Point Dividers, and an MPEG2 Decoder," ISSCC Dig. Tech. Papers, pp. 256-257, 1999.
3. R. Rogenmoser et al., "A Dual-Issue Floating-Point Coprocessor with SIMD Architecture and Fast 3D Functions," ISSCC Dig. Tech. Papers, pp. 414-415, 2002.
4. O. Nishii et al., "A 200MHz 1.2W 1.4GFLOPS Microprocessor with Graphic Operation Unit," ISSCC Dig. Tech. Papers, pp. 288-289, 447, 1998.
5. T. Kamei et al., "A Resume-Standby Application Processor for 3G Cellular Phones," ISSCC Dig. Tech. Papers, pp. 336-337, Feb. 2004.
6. M. S. Schmookler et al., "Leading Zero Anticipation and Detection - a Comparison of Methods," 15th IEEE Symp. on Computer Arithmetic, pp. 7-12, 2001.