Power and area minimization for multidimensional signal processing

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 4, 2007, Pages 922-934

  Marković, Dejan ^a,b   Nikolić, Borivoje ^a,c   Brodersen, Robert W ^a,c  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Circuit optimization; CMOS digital integrated circuits; Design methodology; Field programmable gate arrays; Matrix decomposition; MIMO systems; Multidimensional signal processing; Parallel architectures; Pipelines; Sensitivity

Indexed keywords

CIRCUIT OPTIMIZATION; MATRIX DECOMPOSITION; MULTIDIMENSIONAL SIGNAL PROCESSING; PARALLEL ARCHITECTURES;

ALGORITHMS; GRAPHIC METHODS; MICROPROCESSOR CHIPS; OPTIMIZATION; SENSITIVITY ANALYSIS; WIRELESS LOCAL AREA NETWORKS (WLAN);

SIGNAL PROCESSING;

EID: 33947657010     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.892191     Document Type: Article

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