Asynchronous computing in sense amplifier-based pass transistor logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 7, 2009, Pages 883-892

  Liu, Tsung Te ^a   Alarcon, Louis P ^a   Pierson, Matthew D ^a   Rabaey, Jan M ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

90 nm CMOS; Low leakage circuits; Low voltage circuits; Pass transistor; Self timing; Sense amplifier based pass transistor logic (SAPTL)

Indexed keywords

90-NM CMOS; LOW-LEAKAGE CIRCUITS; LOW-VOLTAGE CIRCUITS; PASS TRANSISTOR; SELF-TIMING; SENSE AMPLIFIER-BASED PASS TRANSISTOR LOGIC (SAPTL);

DECODING; ELECTRIC POTENTIAL; NETWORK ARCHITECTURE; TIME MEASUREMENT; TIMING CIRCUITS; TRANSISTORS;

LOGIC CIRCUITS;

EID: 67651091527     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2012054     Document Type: Conference Paper

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