A 720μW 50MOPs 1V DSP for a hearing aid chip set

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 238-239

  Mosch, P ^a   Van Oerle, G ^a   Menzl, S ^a   Rougnon Glasson, N ^a   Van Nieuwenhove, K ^a   Wezelenburg, M ^a  

^a Xemics SA   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; ADDERS; ALGORITHMS; C (PROGRAMMING LANGUAGE); COMPUTER AIDED SOFTWARE ENGINEERING; DIGITAL SIGNAL PROCESSING; FAST FOURIER TRANSFORMS; HEARING AIDS; MULTIPLYING CIRCUITS; NOISE ABATEMENT; OPTIMIZATION; PATTERN RECOGNITION; SIGNAL ENCODING; THRESHOLD VOLTAGE; TREES (MATHEMATICS);

MULTI-BAND COMPRESSION;

MICROPROCESSOR CHIPS;

EID: 0034430956     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Algorithm and architecture of a 1V low power hearing instrument DSP
2. Low-Power CMOS digital design
3. n DCT and DST algorithms
4. Power optimization of telecom baseband functions using architectural exploration
5. An 85μW asynchronous filter-bank for a digital hearing aid
6. Low-Power low-voltage digital CMOS cell design
7. High speed: Not the only way to exploit the intrinsic computational power of silicon