ESD design challenges and strategies in deeply-scaled integrated circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2009, Pages 681-688

  Cao, Shuqing ^a   Chen, Tze Wee ^a   Beebe, Stephen G ^b   Dutton, Robert W ^a  

^a STANFORD UNIVERSITY   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Charged device model (CDM); Co design methodology; Electrostatic discharge (ESD); Field effect diode; High speed I O; Integrated circuit reliability; Semiconductor diodes; VF TLP

Indexed keywords

CHARGED DEVICE MODEL; CO-DESIGN METHODOLOGY; FIELD EFFECT DIODE; HIGH SPEED I/O; INTEGRATED CIRCUIT RELIABILITY;

CONTINUUM DAMAGE MECHANICS; DESIGN; ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; RELIABILITY; SEMICONDUCTOR DEVICE MODELS; SILICON WAFERS;

SEMICONDUCTOR DIODES;

EID: 74049099042     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2009.5280727     Document Type: Conference Paper

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