Design methodology and protection strategy for ESD-CDM robust digital system design in 90-nm and 130-nm technologies

IEEE Transactions on Electron Devices

Volumn 56, Issue 2, 2009, Pages 275-283

  Chen, Tze Wee ^a,b   Ito, Choshu ^a   Loh, William ^a   Wang, Wei ^b   Doddapaneni, Kalyan ^a   Mitra, Subhasish ^b   Dutton, Robert W ^b  

^a AGERE SYSTEMS   (United States)

^b Stanford University   (United States)

Author keywords

Chip level function failure prediction; ESD charged device model (CDM); Inductive coupling; Postbreakdown transistor macromodel

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CONTINUUM DAMAGE MECHANICS; DESIGN; ELECTROSTATIC DEVICES; FAILURE ANALYSIS; FUNCTIONS; INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; PROBABILITY DENSITY FUNCTION; QUALITY ASSURANCE; SAFETY FACTOR; TRANSISTORS;

CHIP DESIGNS; CHIP-LEVEL FUNCTION FAILURE PREDICTION; CORRECT BY CONSTRUCTIONS; DESIGN METHODOLOGIES; DESIGN TOOLS; DIGITAL SYSTEM DESIGNS; DIGITAL SYSTEMS; ESD-CHARGED DEVICE MODEL (CDM); INDUCTIVE COUPLING; POSTBREAKDOWN TRANSISTOR MACROMODEL; PROTECTION STRATEGIES; RELATED FUNCTIONS; SYSTEM-ON-CHIP DESIGNS;

ELECTROSTATIC DISCHARGE;

EID: 59849112629     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2008.2010586     Document Type: Article

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