-
2
-
-
0028744520
-
Core clamps for low voltage technologies
-
Las Vegas, NV, September
-
Dabral S, Aslett R, Maloney T. Core clamps for low voltage technologies. In: Proceedings of EOS/ESD Symposium, Las Vegas, NV, September 1994. p. 141-9
-
(1994)
Proceedings of EOS/ESD Symposium
, pp. 141-149
-
-
Dabral, S.1
Aslett, R.2
Maloney, T.3
-
3
-
-
0029476615
-
Novel clamp circuits for IC power supply protection
-
Phoenix, AZ, September
-
Maloney T, Dabral S. Novel clamp circuits for IC power supply protection. In: Proceedings of EOS/ESD Symposium, Phoenix, AZ, September 1995. p. 1-12
-
(1995)
Proceedings of EOS/ESD Symposium
, pp. 1-12
-
-
Maloney, T.1
Dabral, S.2
-
4
-
-
0029478654
-
Sub-micron chip ESD protection schemes which avoid avalanching junctions
-
Phoenix, AZ, September
-
Worley E, Gupta R, Jones B, Kjar R, Nguyen C, Tennyson M. Sub-micron chip ESD protection schemes which avoid avalanching junctions. In: Proceedings of EOS/ESD Symposium, Phoenix, AZ, September, 1995. p. 13-20
-
(1995)
Proceedings of EOS/ESD Symposium
, pp. 13-20
-
-
Worley, E.1
Gupta, R.2
Jones, B.3
Kjar, R.4
Nguyen, C.5
Tennyson, M.6
-
5
-
-
0032310094
-
Cross-referenced ESD protection for power supplies
-
Reno, NV, October
-
Anderson W, Montanaro J, Howorth N. Cross-referenced ESD protection for power supplies. In: Proceedings of EOS/ESD Symposium, Reno, NV, October 1998. p. 86-95
-
(1998)
Proceedings of EOS/ESD Symposium
, pp. 86-95
-
-
Anderson, W.1
Montanaro, J.2
Howorth, N.3
-
6
-
-
84948960517
-
Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies
-
Portland, OR, September
-
Torres C, Miller J, Stockinger M, Akers M, Khazhinsky M, Weldon J. Modular, portable, and easily simulated ESD protection networks for advanced CMOS technologies. In: Proceedings of EOS/ESD Symposium, Portland, OR, September 2001. p. 82-95
-
(2001)
Proceedings of EOS/ESD Symposium
, pp. 82-95
-
-
Torres, C.1
Miller, J.2
Stockinger, M.3
Akers, M.4
Khazhinsky, M.5
Weldon, J.6
-
7
-
-
11344283347
-
-
Electrostatic discharge (ESD) protection circuit. US Patent No. 6,385,021 B1, May
-
Takeda F, Miller J. Electrostatic discharge (ESD) protection circuit. US Patent No. 6,385,021 B1, May 2002
-
(2002)
-
-
Takeda, F.1
Miller, J.2
-
8
-
-
11344266618
-
-
Patent application filed with the USPTO
-
Miller J, Hall G, Krasin A, Stockinger M, Akers M, Kamat V. Patent application filed with the USPTO
-
-
-
Miller, J.1
Hall, G.2
Krasin, A.3
Stockinger, M.4
Akers, M.5
Kamat, V.6
-
9
-
-
17644440986
-
A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications
-
San Francisco, CA, December
-
Perera AH, Smith B, Cave N, Sureddin M, Chheda S, Islam R, et al. A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications. In: Proceedings of International Electron Devices Meeting, IEDM 2000, San Francisco, CA, December 2000. p. 571-4
-
(2000)
Proceedings of International Electron Devices Meeting, IEDM 2000
, pp. 571-574
-
-
Perera, A.H.1
Smith, B.2
Cave, N.3
Sureddin, M.4
Chheda, S.5
Islam, R.6
-
10
-
-
0036045178
-
A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power. High performance and RF/analog system on chip applications
-
Honolulu, HI, June
-
Yeap GC-F, Chen J, Grudowski P, Jeon Y, Shiho Y, Qi W, et al. A 100 nm copper/low-K bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power. High performance and RF/analog system on chip applications. In: Proceedings of Symposium on VLSI Technology, Honolulu, HI, June 2002. p. 16-7
-
(2002)
Proceedings of Symposium on VLSI Technology
, pp. 16-17
-
-
Yeap, G.C.-F.1
Chen, J.2
Grudowski, P.3
Jeon, Y.4
Shiho, Y.5
Qi, W.6
-
11
-
-
0020205140
-
An analytical breakdown model for short-channel MOSFET's
-
Hsu F., Ko P., Tam S., Hu C., Mulle R. An analytical breakdown model for short-channel MOSFET's. IEEE Trans. Electron Devices. 29:1982;1735-1740
-
(1982)
IEEE Trans. Electron Devices
, vol.29
, pp. 1735-1740
-
-
Hsu, F.1
Ko, P.2
Tam, S.3
Hu, C.4
Mulle, R.5
-
13
-
-
0028752365
-
ESD trigger circuit
-
Las Vegas, NV, September
-
Tandan N. ESD trigger circuit. In: Proceedings of EOS/ESD Symposium, Las Vegas, NV, September 1994. p. 120-4
-
(1994)
Proceedings of EOS/ESD Symposium
, pp. 120-124
-
-
Tandan, N.1
-
14
-
-
0033279088
-
Stacked PMOS clamps for high voltage power supply protection
-
Orlando, FL, September
-
Maloney T, Kan W. Stacked PMOS clamps for high voltage power supply protection. In: Proceedings of EOS/ESD Symposium, Orlando, FL, September 1999. p. 70-7
-
(1999)
Proceedings of EOS/ESD Symposium
, pp. 70-77
-
-
Maloney, T.1
Kan, W.2
-
15
-
-
84948757566
-
New considerations for MOSFET power clamps
-
Charlotte, NC, October
-
Poon S, Maloney T. New considerations for MOSFET power clamps. In: Proceedings of EOS/ESD Symposium, Charlotte, NC, October 2002. p. 1-5
-
(2002)
Proceedings of EOS/ESD Symposium
, pp. 1-5
-
-
Poon, S.1
Maloney, T.2
-
16
-
-
11344295905
-
-
Circuit for electrostatic discharge protection. US Patent No. 5946177, August
-
Miller J, Torres C, Cooper T. Circuit for electrostatic discharge protection. US Patent No. 5946177, August 1999
-
(1999)
-
-
Miller, J.1
Torres, C.2
Cooper, T.3
-
17
-
-
11344261006
-
-
Patent application filed with the USPTO
-
Stockinger M, Miller J. Patent application filed with the USPTO
-
-
-
Stockinger, M.1
Miller, J.2
-
18
-
-
84948994333
-
Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling
-
Portland, OR, September
-
Mergens M, Verhaege K, Russ C, Armer J, Jozwiak P, Kolluri G, et al. Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling. In: Proceedings of EOS/ESD Symposium, Portland, OR, September 2001. p. 1-11
-
(2001)
Proceedings of EOS/ESD Symposium
, pp. 1-11
-
-
Mergens, M.1
Verhaege, K.2
Russ, C.3
Armer, J.4
Jozwiak, P.5
Kolluri, G.6
-
19
-
-
84875290566
-
High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation
-
Charlotte, NC, October
-
Mergens M, Russ C, Verhaege K, Armer J, Jozwiak P, Mohn R. High holding current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation. In: Proceedings of EOS/ESD Symposium, Charlotte, NC, October 2002. p. 10-7
-
(2002)
Proceedings of EOS/ESD Symposium
, pp. 10-17
-
-
Mergens, M.1
Russ, C.2
Verhaege, K.3
Armer, J.4
Jozwiak, P.5
Mohn, R.6
|