Advanced metallization for 3D integration

10th Electronics Packaging Technology Conference, EPTC 2008

Volumn , Issue , 2008, Pages 212-218

  Beica, Rozalia ^a   Siblerud, Paul ^a   Sharbono, Charles ^a   Bernt, Marvin ^a  

^a Semitool Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATIONS; APPROXIMATION THEORY; ASPECT RATIO; CHEMICAL ENGINEERING; CHIP SCALE PACKAGES; COST REDUCTION; DEPOSITION; ELECTRIC CONDUCTIVITY; ELECTRODEPOSITION; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS INDUSTRY; LITHOGRAPHY; METALLIZING; OPTICAL INTERCONNECTS; PACKAGING; PHOTORESISTS; PHYSICAL VAPOR DEPOSITION; PRESSURE DROP; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR MATERIALS; SILICON WAFERS; STRUCTURAL METALS; TECHNOLOGY; VAPORS;

3-D INTEGRATIONS; 3-D INTERCONNECTS; 3-D PACKAGING; 3D VERTICAL INTEGRATIONS; ADVANCED PACKAGING; CHEMICAL FORMULATIONS; CHIP STACKING; CONDUCTIVE LAYERS; COPPER ELECTRODEPOSITIONS; COPPER INTERCONNECT; DEPOSITION CONDITIONS; DEPOSITION METHODS; ELECTRODEPOSITION PROCESS; ELECTRONIC PRODUCTS; FORM FACTORS; HIGH ASPECT RATIOS; LOWER COSTS; MATERIALS AND PROCESS; METALLIZATION; NEW APPROACHES; NEW TECHNOLOGIES; PACKAGING TECHNOLOGIES; PROCESS PARAMETERS; REDISTRIBUTION LAYERS; RESEARCH INSTITUTES; SEED LAYERS; SEMICONDUCTOR INDUSTRIES; SEMICONDUCTOR MANUFACTURERS; THICKNESS DISTRIBUTIONS; THROUGH MASKS; THROUGH-SILICON-VIA; VIA FILLINGS; VOID-FREE; WAFER-LEVEL PACKAGING; WET CHEMICAL PROCESS; WITHIN DIES;

CHEMICAL VAPOR DEPOSITION;

EID: 63049135175     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2008.4763436     Document Type: Conference Paper

References (12)

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8. th Electronic Components and Technology Conference, Orlando, May 2008
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11. st International Wafer Level packaging Congress, 2004
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