Frequency and yield optimization using power gates in power-constrained designs

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2009, Pages 121-126

  Nam, Sung Kim ^a   Jun, Seomun ^b   Sinkar, Abhishek ^a   Jungseob, Lee ^a   Tae, Hee Han ^c   Ken, Choi ^d   Youngsoo, Shin ^b  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^c Sungkyunkwan University   (South Korea)

^d ILLINOIS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Frequency; Optimization; Power gate; Yield

Indexed keywords

ACTIVE LEAKAGE; BENCHMARK CIRCUIT; CONSTRAINED DESIGN; DIFFERENT FREQUENCY; FREQUENCY BINNING; FREQUENCY OPTIMIZATION; FREQUENCY REGIONS; HIGHER FREQUENCIES; LEAKAGE POWER; MAXIMUM FREQUENCY; MAXIMUM OPERATING FREQUENCY; MULTI-CORE PROCESSOR; OPTIMIZATION METHOD; POWER CONSTRAINTS; PROCESS VARIATION; SUPPLY VOLTAGES; TECHNOLOGY SCALING; TOTAL POWER CONSUMPTION; WITHIN-DIE VARIATIONS; YIELD OPTIMIZATION;

DESIGN; DIES; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; LOW POWER ELECTRONICS; MICROPROCESSOR CHIPS; POWER ELECTRONICS;

CONSTRAINED OPTIMIZATION;

EID: 70449704651     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1594233.1594263     Document Type: Conference Paper

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