Decoupled store completion/silent deterministic replay: Enabling scalable data memory for CPR/CFP processors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2009, Pages 245-254

  Hilton, Andrew ^a   Roth, Amir ^a  

^a UNIVERSITY OF PENNSYLVANIA   (United States)

Author keywords

Checkpoint processors; Load store queues

Indexed keywords

ADAPTIVE INSTRUCTION; CACHE MISS; DATA MEMORY; IN-FLIGHT INSTRUCTIONS; IN-FLIGHT STORES; LOAD QUEUE; LOAD-STORE QUEUE; MEMORY ORDERING; MEMORY SYSTEMS; MIS-SPECULATION RECOVERY; REGISTER FILES;

BUFFER STORAGE; COMPUTER ARCHITECTURE; COMPUTERS; INFORMATION RETRIEVAL; ION BEAMS; PIPELINE PROCESSING SYSTEMS; QUEUEING THEORY; WINDOWS;

RETAIL STORES;

EID: 70449695080     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1555754.1555786     Document Type: Conference Paper

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