On the latency, energy and area of checkpointed, superscalar register alias tables

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2007, Pages 379-382

  Safi, Elham ^a   Akl, Patrick ^a   Moshovos, Andreas ^a   Veneris, Andreas ^a   Arapoyianni, Aggeliki ^b  

^a UNIVERSITY OF TORONTO   (Canada)

^b UNIVERSITY OF ATHENS   (Greece)

Author keywords

Checkpointing; Energy; Latency; Register renaming

Indexed keywords

CHECKPOINTING; GLOBAL CHECKPOINTS (GC); REGISTER ALIAS TABLES (RAT); REGISTER RENAMING;

BUFFER STORAGE; ELECTRIC POWER UTILIZATION; SHIFT REGISTERS;

CMOS INTEGRATED CIRCUITS;

EID: 37048999761     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1283780.1283863     Document Type: Conference Paper

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