Mutual exploration of FinFET technology and circuit design options for implementing compact brute-force latches

2009 1st Asia Symposium on Quality Electronic Design, ASQED 2009

Volumn , Issue , 2009, Pages 1-8

  Tawfik, Sherif A ^a   Kursun, Volkan ^b  

^a Wisconsin Electric Machines and Power Electronics Consortium   (United States)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE MODE; BRUTE FORCE; CIRCUIT DESIGNS; CIRCUIT TOPOLOGY; ENGINEERING TECHNIQUES; GATE BIAS; GATE TRANSISTORS; GATE UNDERLAP; LAYOUT AREA; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW POWER; MULTITHRESHOLD; POWER CONSUMPTION; PROCESSING STEPS; PROPAGATION DELAYS; SET-UP TIME; STATIC NOISE MARGIN; TECHNOLOGY OPTIONS;

ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENGINEERING; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT MANUFACTURE;

FLIP FLOP CIRCUITS;

EID: 70449511222     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASQED.2009.5206309     Document Type: Conference Paper

References (16)

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