Leakage-aware design of nanometer SoC

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3231-3234

  Kursun, Volkan ^a   Tawfik, Sherif A ^a   Liu, Zhiyu ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATE DIELECTRICS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOSFET DEVICES; THRESHOLD VOLTAGE;

ENERGY REDUCTION; NANOMETER SOC; NOISE IMMUNITY; OXIDE-THICKNESS;

MICROPROCESSOR CHIPS;

EID: 34548853435     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378160     Document Type: Conference Paper

References (6)

1. V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, John Wiley & Sons Ltd., 2006, ISBN # 0-470-01023-1.
2. S. Mutoh et al., "1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS," IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, pp. 847-853, August 1995.
3. S. Shigematsu et al., "A 1-V High-Speed MTCMOS Circuit Scheme for Power-Down Application Circuits," IEEE Journal of Solid-State Circuits, Vol. 32, No. 6. pp. 861-869, June 1997.
4. [41 Z. Liu and V. Kursun, "Leakage Biased pMOS Sleep Switch Dynamic Circuits," IEEE Transactions on Circuits and Systems II, Vol. 53, No. 10. pp. 1093-1097, October 2006.
5. [51 Predictive Technology Model, http://www.eas.asu.edu/~ptm/.
6. Taurus Medici Device Simulator, Synopsis, Inc., 2003.