Multi-Vth finFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 348-351

  Tawfik, Sherif A ^a   Kursun, Volkan ^b  

^a Wisconsin Electric Machines and Power Electronics Consortium   (United States)

^b HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

FINFETS; GATE BIAS; LEAKAGE POWER; NOISE IMMUNITIES; POWER CONSUMPTION; REDUCED POWER CONSUMPTION; WORK-FUNCTION;

ELECTRIC POWER UTILIZATION; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUITS; SEQUENTIAL CIRCUITS; THRESHOLD VOLTAGE;

FLIP FLOP CIRCUITS;

EID: 62949153976     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746031     Document Type: Conference Paper

References (8)

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6. S. A. Tawfik and V. Kursun, "Low-Power and Compact Sequential Circuits with Independent-Gate FinFETs," IEEE Transactions on Electron Devices, Vol. 55, Number 1, pp. 60-70, January 2008.
7. Y. Liu et al., "Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs with Asymmetric Gate-Oxide Thicknesses," IEEE Electron Device Letters, Vol. 28, No. 6, pp. 517-519, June 2007.
8. S. A. Tawfik and V. Kursun, "Work-Function Engineering for Reduced Power and Higher Integration Density: An Alternative to Sizing for Stability in FinFET Memory Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 788-791, May 2008.