Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2008, Pages 788-791

  Tawfik, Sherif A ^a   Kursun, Volkan ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER NETWORKS; RANDOM ACCESS STORAGE; TECHNICAL PRESENTATIONS; THRESHOLD VOLTAGE;

INTERNATIONAL SYMPOSIUM; MEMORY ARRAYS; WORK FUNCTIONS;

SYSTEM STABILITY;

EID: 51749107243     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2008.4541536     Document Type: Conference Paper

References (6)

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2. R. Lin et al., "An Adjustable Work Function Technology Using Mo Gate for CMOS Devices," IEEE Electron Device Letters, Vol. 23, No. 1, pp. 49-51, January 2002.
3. P. Ranade et al., "Work Function Engineering of Molybdenum Gate Electrodes by Nitrogen Implantation," Electrochemical and Solid-State Letters, Vol. 4, Issue 11, pp. G85-G87, November 2001.
4. J. Kedzierski et al., "Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation," Proceedings of the IEEE Electron Devices Meeting, pp. 247-250, December 2002.
5. E. Seevinck, F. J. List, and J. Lohstroh, "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. 22, No. 5, pp. 748-754, October 1987.
6. Medici Device Simulator, Synopsys, Inc., 2006.