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Volumn , Issue , 2009, Pages 246-251

Parameter space exploration for robust and high-performance n-channel and p-channel symmetric double-gate FinFETs

Author keywords

[No Author keywords available]

Indexed keywords

DEVICE PARAMETERS; DOUBLE-GATE; ELECTRICAL CHARACTERISTIC; FIN THICKNESS; FINFETS; GATE LENGTH; GATE OXIDE; N-CHANNEL; ON-CURRENTS; PARAMETER SPACES; ROOM TEMPERATURE; SUBTHRESHOLD;

EID: 70449510191     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASQED.2009.5206260     Document Type: Conference Paper
Times cited : (4)

References (13)
  • 1
    • 18844457099 scopus 로고    scopus 로고
    • Leakage power analysis of 25-nm double-gate CMOS devices and circuits
    • May
    • K. Kim et al., "Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits," IEEE Transactions on Electron Devices, Vol.52, No.5, pp. 980-986, May 2005.
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.5 , pp. 980-986
    • Kim, K.1
  • 2
    • 39549086683 scopus 로고    scopus 로고
    • Investigation of FinFET Devices for 32nm Technologies and beyond
    • June
    • H. Shang et al., "Investigation of FinFET Devices for 32nm Technologies and Beyond," Proceedings of the IEEE Symposium on VLSI Technology, pp. 54-55, June 2006.
    • (2006) Proceedings of the IEEE Symposium on VLSI Technology , pp. 54-55
    • Shang, H.1
  • 3
    • 1842865629 scopus 로고    scopus 로고
    • Turning Silicon on Its Edge
    • January/February
    • E. Nowak et al., "Turning Silicon on Its Edge," IEEE Circuits & Devices Magazine, Vol.20, No.1, pp. 20-31, January/February 2004.
    • (2004) IEEE Circuits & Devices Magazine , vol.20 , Issue.1 , pp. 20-31
    • Nowak, E.1
  • 4
    • 37749005263 scopus 로고    scopus 로고
    • Low-Power and Compact Sequential Circuits with Independent-Gate FinFETs
    • January
    • S. A. Tawfik and V. Kursun, "Low-Power and Compact Sequential Circuits with Independent-Gate FinFETs," IEEE Transactions on Electron Devices, Vol.55, No.1, pp. 60-70, January 2008.
    • (2008) IEEE Transactions on Electron Devices , vol.55 , Issue.1 , pp. 60-70
    • Tawfik, S.A.1    Kursun, V.2
  • 5
    • 3042657475 scopus 로고    scopus 로고
    • Synopsys Inc. February
    • Medici Device Simulator, Synopsys, Inc., February 2003.
    • (2003) Medici Device Simulator
  • 6
    • 33750588894 scopus 로고    scopus 로고
    • Leakage biased PMOS sleep switch dynamic circuits
    • October
    • Z. Liu and V. Kursun, "Leakage Biased PMOS Sleep Switch Dynamic Circuits," IEEE Transactions on Circuits and Systems II, Vol.53, No.10, pp. 1093 - 1097, October 2006.
    • (2006) IEEE Transactions on Circuits and Systems II , vol.53 , Issue.10 , pp. 1093-1097
    • Liu, Z.1    Kursun, V.2
  • 7
    • 8144223889 scopus 로고    scopus 로고
    • Metal gate work function engineering on gate leakage of MOSFETs
    • November
    • Y. T. Hou, M. F. Li, T. Low, and D. L. Kwong, "Metal Gate Work Function Engineering on Gate Leakage of MOSFETs," IEEE Transactions on Electron Devices, Vol.51, No.11, pp. 1783- 1789, November 2004.
    • (2004) IEEE Transactions on Electron Devices , vol.51 , Issue.11 , pp. 1783-1789
    • Hou, Y.T.1    Li, M.F.2    Low, T.3    Kwong, D.L.4
  • 10
  • 11
    • 51749107243 scopus 로고    scopus 로고
    • Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits
    • May
    • S. A. Tawfik and V. Kursun, "Work-Function Engineering for Reduced Power and Higher Integration Density: An Alternative to Sizing for Stability in FinFET Memory Circuits," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 788-791, May 2008.
    • (2008) Proceedings of the IEEE International Symposium on Circuits and Systems , pp. 788-791
    • Tawfik, S.A.1    Kursun, V.2
  • 12
    • 62949153976 scopus 로고    scopus 로고
    • Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption
    • December
    • S. A. Tawfik and V. Kursun, "Multi-Vth FinFET Sequential Circuits with Independent-Gate Bias and Work-Function Engineering for Reduced Power Consumption," Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, December 2008.
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    • Tawfik, S.A.1    Kursun, V.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.