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Volumn , Issue , 2008, Pages 855-860

Compact FinFET memory circuits with p-type data access transistors for low leakage and robust operation

Author keywords

[No Author keywords available]

Indexed keywords

CROSS-COUPLED; DATA ACCESS; DATA STORAGE; ELECTRONIC DESIGNS; IDLE MODE; INTEGRATION DENSITIES; INTERNATIONAL SYMPOSIUM; LEAKAGE POWER; LEAKAGE POWER CONSUMPTION; LOW LEAKAGE; MEMORY CIRCUITS; MINIMUM-SIZED TRANSISTORS; READ OPERATIONS; READ STABILITY; ROBUST OPERATION; SRAM CELLS; VOLTAGE DISTURBANCES;

EID: 49749139400     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479850     Document Type: Conference Paper
Times cited : (14)

References (11)
  • 1
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    • January/February
    • E. Nowak et al., "Turning Silicon on Its Edge," IEEE Circuits & Devices Magazine, pp. 20-31, January/February 2004.
    • (2004) IEEE Circuits & Devices Magazine , pp. 20-31
    • Nowak, E.1
  • 2
    • 34249803816 scopus 로고    scopus 로고
    • Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs with Asymmetric Gate-Oxide Thicknesses
    • June
    • Y. Liu et al., "Cointegration of High-Performance Tied-Gate Three-Terminal FinFETs and Variable Threshold-Voltage Independent-Gate Four-Terminal FinFETs with Asymmetric Gate-Oxide Thicknesses," IEEE Electron Device Letters, Vol. 28, No. 6, pp. 517-519, June 2007.
    • (2007) IEEE Electron Device Letters , vol.28 , Issue.6 , pp. 517-519
    • Liu, Y.1
  • 3
    • 18044390851 scopus 로고    scopus 로고
    • 4-Terminal FinFETs with High Threshold Voltage Controllability
    • June
    • Y. X. Liu et al., "4-Terminal FinFETs with High Threshold Voltage Controllability," Proceedings of the IEEE Device Research Conference, Vol. 1, pp. 207-208, June 2004.
    • (2004) Proceedings of the IEEE Device Research Conference , vol.1 , pp. 207-208
    • Liu, Y.X.1
  • 4
    • 0036923594 scopus 로고    scopus 로고
    • Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation
    • December
    • J. Kedzierski et al., "Metal-gate FinFET and Fully-Depleted SOI Devices Using Total Gate Silicidation,"Proceedings of the IEEE Electron Devices Meeting, pp. 247-250, December 2002.
    • (2002) Proceedings of the IEEE Electron Devices Meeting , pp. 247-250
    • Kedzierski, J.1
  • 7
    • 4544347719 scopus 로고    scopus 로고
    • Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology
    • June
    • M. Yamaoka et al., "Low Power SRAM Menu for SOC Application Using Yin-Yang-Feedback Memory Cell Technology," Proceedings of the IEEE Symposium on VLSI Circuits, pp. 288-291, June 2004.
    • (2004) Proceedings of the IEEE Symposium on VLSI Circuits , pp. 288-291
    • Yamaoka, M.1
  • 8
    • 34548818512 scopus 로고    scopus 로고
    • A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation
    • May
    • B. Giraud et al., "A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3022-3025, May 2007.
    • (2007) Proceedings of the IEEE International Symposium on Circuits and Systems , pp. 3022-3025
    • Giraud, B.1
  • 9
    • 49749145922 scopus 로고    scopus 로고
    • Medici Device Simulator, Synopsys, Inc., 2006.
    • Medici Device Simulator, Synopsys, Inc., 2006.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.