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Volumn , Issue , 2007, Pages 63-66

An independent-gate FinFET SRAM cell for high data stability and enhanced integration density

Author keywords

Active power; Cache memory; Data stability; Double gate mosfet; Standby power; Static noise margin

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; CYTOLOGY; NETWORKS (CIRCUITS); PROGRAMMABLE LOGIC CONTROLLERS; STANDARDS; TRANSISTORS;

EID: 49749147773     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCC.2007.4545427     Document Type: Conference Paper
Times cited : (24)

References (10)
  • 1
    • 1842865629 scopus 로고    scopus 로고
    • Turning Silicon on Its Edge
    • January/February
    • E. Nowak et al., "Turning Silicon on Its Edge," IEEE Circuits & Device Magazine, pp. 20-31, January/February 2004.
    • (2004) IEEE Circuits & Device Magazine , pp. 20-31
    • Nowak, E.1
  • 2
    • 39549086683 scopus 로고    scopus 로고
    • Investigation of FinFET Devices for 32nm Technologies and Beyond
    • June
    • H. Shang et al., "Investigation of FinFET Devices for 32nm Technologies and Beyond," Proceedings of the IEEE Symposium on VLSI Technology, pp. 54-55, June 2006.
    • (2006) Proceedings of the IEEE Symposium on VLSI Technology , pp. 54-55
    • Shang, H.1
  • 3
    • 20144387099 scopus 로고    scopus 로고
    • CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)
    • October
    • L. Mathew et al., "CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)," Proceedings of the IEEE International SOI Conference, pp.187-189, October 2004.
    • (2004) Proceedings of the IEEE International SOI Conference , pp. 187-189
    • Mathew, L.1
  • 4
    • 0142185837 scopus 로고    scopus 로고
    • S. Mitra et al., Low Voltage/Low Power Sub 50nm Double Gate SOI Ratioed Logic, Proceedings of the IEEE International SOI Conference, pp.177-178, September 2003.
    • S. Mitra et al., "Low Voltage/Low Power Sub 50nm Double Gate SOI Ratioed Logic," Proceedings of the IEEE International SOI Conference, pp.177-178, September 2003.
  • 5
    • 33947117331 scopus 로고    scopus 로고
    • High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices
    • September
    • M-H. Chiang et al., "High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices," IEEE Transactions on Electron Devices, Vol. 53, No. 9, pp. 2370-2377, September 2006.
    • (2006) IEEE Transactions on Electron Devices , vol.53 , Issue.9 , pp. 2370-2377
    • Chiang, M.-H.1
  • 8
    • 51049092720 scopus 로고    scopus 로고
    • Medici Device Simulator, Synopsys, Inc., 2006.
    • Medici Device Simulator, Synopsys, Inc., 2006.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.