Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 2008, Pages 20-21

  Yang, J W ^a   Harris, H R ^b   Hussain, M M ^a   Sassman, B ^a   Tseng, H H ^a   Jammy, R ^c  

^a SEMATECH   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FIELD EFFECT TRANSISTORS; SECURITY SYSTEMS; TECHNOLOGY;

32 NM TECHNOLOGY; DEVICE PERFORMANCES; DOUBLE GATES; ENHANCED PERFORMANCE; FINFETS; GATE - SOURCE/DRAIN UNDERLAP; INTERNATIONAL SYMPOSIUM; PROCESS STEPS; SRAM STABILITY; STATIC-NOISE MARGIN; VLSI TECHNOLOGIES;

STATIC RANDOM ACCESS STORAGE;

EID: 49049094613     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2008.4530779     Document Type: Conference Paper

References (6)

1. J.-W. Yang, et al., IEEE Trans. Electron Devices, pp.1464, June 2007
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3. J. G. Fossum, et al., IEEE IEDM Tech. dig., pp.679-682, Dec. 2003
4. C. Y. Rang, et al., IEEE IEDM Tech. dig., pp.885, Dec. 2006
5. J. G. Fossum, et al., IEEE Trans. Electron Devices, pp.808, May 2002
6. A. Bansal, et al., IEEE Trans. Electron Devices, pp.1409, June 2007