Continuous time sigma delta modulator employing a novel comparator architecture

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 919-924

  Vijay, U K ^a   Bharadwaj, Amrutur ^a  

^a INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR ARCHITECTURE; CONTINUOUS-TIME (CT); DYNAMIC RANGE (DR); ENTIRE SYSTEM; EXCESS LOOP DELAY; HIGH SPEED OPERATIONS; INTERNATIONAL CONFERENCES; LOW-VOLTAGE (LV); PERFOR MANCE COMPARISON; PERFORMANCE ENHANCEMENTS; QUANTIZER; SIGMA DELTA MODULATOR (SDM); SINGLE POLY; SPEED UPS; VLSI DESIGNS;

CMOS INTEGRATED CIRCUITS; COMPARATORS (OPTICAL); COMPUTER PROGRAMMING LANGUAGES; CONTINUOUS TIME SYSTEMS; DELTA SIGMA MODULATION; INTEGRATED CIRCUITS; METALS; MODULATORS; MULTICARRIER MODULATION; SPEED; STANDARDS;

EMBEDDED SYSTEMS;

EID: 48349091329     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.54     Document Type: Conference Paper

References (8)

1. IEEE 802.15.4: Wireless MAC and Physical Layer (PHY) specification for LR-WPANs.
2. Shouli Yan et al., "A continuous time Sigma-delta modulator with 88-dB dynamic range and 1.1 MHz signal bandwidth", IEEE J. Solid-State Circuits, vol. 39, pp. 75-86, Jan 2004.
3. James A. Cherry et al., "Continuous time Delta-Sigma modulators for high speed A/D conversion", Kluwer Academic publishers, 1999.
4. Richard Scherier, MIT open course-ware: High-Speed Communication Circuits and Systems, MIT.
5. Michael S. Kappes, "A 2.2mW CMOS bandpass continuous time multi-bit Delta-Sigma ADC with 68 dB of dynamic range and 1 MHz bandwidth for wireless applications", IEEE J. Solid-State Circuits, vol. 38, pp. 1098-1104, July. 2003.
6. nd ed., Kluwer academic publishers, 2003.
7. Richard Scherier et.al, "Delta-Sigma data converters: Theory, Design and Simulation", IEEE Press, 1996.
8. A. Yukawa, "A CMOS 8-bit high speed A/D converter IC", IEEE J. Solid-State Circuits, vol. SC-20, pp. 775-779, June 1985.