Bridging DFM analysis and volume diagnostics for yield learning - A case study

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2009, Pages 167-172

  Turakhia, Ritesh ^a   Ward, Mark ^a   Goel, Sandeep Kumar ^b   Benware, Brady ^c  

^a LSI Corporation   (United States)

^b AGERE SYSTEMS   (United States)

^c MENTOR GRAPHICS CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-LEVEL; COMPARATIVE ANALYSIS; CONVENTIONAL TECHNIQUES; DESIGN FLOWS; DFM ANALYSIS; RATE PREDICTIONS; SYSTEMATIC YIELD; YIELD LEARNING;

RESEARCH;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 70350417471     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2009.37     Document Type: Conference Paper

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