Question: DRC or DfM? Answer: FMEA and ROI

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 789-794

  Balasinski, Artur ^a  

^a CYPRESS SEMICONDUCTOR   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN RULE CHECKS; DESIGN VERIFICATION; DESIGN-FOR-MANUFACTURABILITY; DETECTABILITY; FAILURE MODE AND EFFECT ANALYSIS; INDIVIDUAL DEVICES; PROFIT MARGIN; SYSTEM ON CHIPS;

MACHINE DESIGN; PROFITABILITY;

FAILURE MODES;

EID: 84886743422     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.110     Document Type: Conference Paper

References (7)

1. C.Guardiani et al., An Effective DfM Strategy Requires Accurate Process and IP Pre-characterization, Design Automation Conference, DAC-2005, Anaheim, CA, p. 760.
2. FMEA Reference Guide, http://www.qualitytrainingportal.com/books- consulting/46a-ref. htm
3. A. Imai et al., Requirements for mask technology from the viewpoint of SoC and Flash memory trends, Proc. Photomask Japan, Yokohama, April 13-15, 2005, pp. 1-2.
4. A.Balasinski, Optimization of sub-100-nm designs for mask cost reduction, Journal of Microlithography, Microfabrication, and Microsystems, vol.3, no.2, pp.322-331, April 2004.
5. Yield Enhancement, ITRS Roadmap, 2003.
6. http://www.valuebasedmanagement.net/methods-roi.html
7. W.Iandolo et al., Optimization of Dummy Pattern for Mask Data Size Reduction, Proc. SPIE, vol. 5256, pp. 798-805, 2003.